From: Zhao Liu Date: Mon, 15 Dec 2025 07:37:43 +0000 (+0800) Subject: dosc/cpu-models-x86: Add documentation for DiamondRapids X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b3104e721b8f163a005e8420faff8ac9f2fc36ca;p=thirdparty%2Fqemu.git dosc/cpu-models-x86: Add documentation for DiamondRapids Current DiamondRapids hasn't supported cache model. Instead, document its special CPU & cache topology to allow user emulate with "-smp" & "-machine smp-cache". Reviewed-by: Yu Chen Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20251215073743.4055227-12-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc index 6a770ca835..3605d05a8c 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration compatibility is required, use the newest CPU model that is compatible across all desired hosts. +``DiamondRapids`` + Intel Xeon Processor. + + Diamond Rapids product has a topology which differs from previous Xeon + products. It does not support SMT, but instead features a dual core + module (DCM) architecture. It also has core building blocks (CBB - die + level in CPU topology). The cache hierarchy is organized as follows: + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per + CBB. This cache topology can be emulated for DiamondRapids CPU model + using the smp-cache configuration as shown below: + + Example: + + :: + + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ + smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ + smp-cache.2.cache=l2,smp-cache.2.topology=module,\ + smp-cache.3.cache=l3,smp-cache.3.topology=die + ``ClearwaterForest`` Intel Xeon Processor (ClearwaterForest, 2025)