From: Sean Christopherson Date: Tue, 1 Apr 2025 16:34:45 +0000 (-0700) Subject: KVM: VMX: Isolate pure loads from atomic XCHG when processing PIR X-Git-Tag: v6.16-rc1~78^2~7^2~2 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b41f8638b9d30fbe045b4ef83ff4136c56a57397;p=thirdparty%2Flinux.git KVM: VMX: Isolate pure loads from atomic XCHG when processing PIR Rework KVM's processing of the PIR to use the same algorithm as posted MSIs, i.e. to do READ(x4) => XCHG(x4) instead of (READ+XCHG)(x4). Given KVM's long-standing, sub-optimal use of 32-bit accesses to the PIR, it's safe to say far more thought and investigation was put into handling the PIR for posted MSIs, i.e. there's no reason to assume KVM's existing logic is meaningful, let alone superior. Matching the processing done by posted MSIs will also allow deduplicating the code between KVM and posted MSIs. See the comment for handle_pending_pir() added by commit 1b03d82ba15e ("x86/irq: Install posted MSI notification handler") for details on why isolating loads from XCHG is desirable. Suggested-by: Jim Mattson Link: https://lore.kernel.org/r/20250401163447.846608-7-seanjc@google.com Signed-off-by: Sean Christopherson --- diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 8b90a537f6ad4..bc56775426c90 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -657,7 +657,7 @@ static u8 count_vectors(void *bitmap) bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr) { - unsigned long pir_vals[NR_PIR_WORDS]; + unsigned long pir_vals[NR_PIR_WORDS], pending = 0; u32 *__pir = (void *)pir_vals; u32 i, vec; u32 irr_val, prev_irr_val; @@ -668,6 +668,13 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr) for (i = 0; i < NR_PIR_WORDS; i++) { pir_vals[i] = READ_ONCE(pir[i]); + pending |= pir_vals[i]; + } + + if (!pending) + return false; + + for (i = 0; i < NR_PIR_WORDS; i++) { if (!pir_vals[i]) continue;