From: Alan Modra <amodra@gmail.com>
Date: Sun, 17 Feb 2019 03:01:41 +0000 (+1030)
Subject: [RS6000] Fix <bd>_<mode> and <bd>tf_<mode> splitters
X-Git-Tag: basepoints/gcc-10~1119
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b43e6340c80f3ae0ddf70950a8f979f4791c3252;p=thirdparty%2Fgcc.git

[RS6000] Fix <bd>_<mode> and <bd>tf_<mode> splitters

This patch fixes a bug that can result in "insn does not satisfy its
constraints" if these splitters fire due to not getting ctr for the
jump insn.  Since the jump insn can have any of r,m,d,wi,c,l as the
decremented count output, it's not sufficient to check for
gpc_reg_operand (which matches VSX regs for example).  Seen after
correcting register_move_cost when the cost of gpr <-> vsx is much
lower.  Since this is a prerequisite to fixing PR89271, I'm mentioning
that PR in the ChangeLog.

The <bd>tf_<mode> split had a further bug in that it wouldn't match
if the count output was m,d,wi, or l.

	PR target/89271
	* config/rs6000/rs6000.md (<bd>_<mode> split): Check for an int
	output reg on add insn.
	(<bd>tf_<mode> split): Likewise.  Match predicates with insn.

From-SVN: r268968
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d80e4f46e5aa..74f96a29089b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-02-17  Alan Modra  <amodra@gmail.com>
+
+	PR target/89271
+	* config/rs6000/rs6000.md (<bd>_<mode> split): Check for an int
+	output reg on add insn.
+	(<bd>tf_<mode> split): Likewise.  Match predicates with insn.
+
 2019-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/89372
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5bca96b70d13..584b9da6e717 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -12588,7 +12588,7 @@
 				const0_rtx);
   emit_insn (gen_rtx_SET (operands[3],
 			  gen_rtx_COMPARE (CCmode, operands[1], const1_rtx)));
-  if (gpc_reg_operand (operands[0], <MODE>mode))
+  if (int_reg_operand (operands[0], <MODE>mode))
     emit_insn (gen_add<mode>3 (operands[0], operands[1], constm1_rtx));
   else
     {
@@ -12666,7 +12666,7 @@
 		       (const_int 0)]))
 	  (match_operand 4)
 	  (match_operand 5)))
-   (set (match_operand:P 6 "int_reg_operand")
+   (set (match_operand:P 6 "nonimmediate_operand")
 	(plus:P (match_dup 0)
 		(const_int -1)))
    (clobber (match_scratch:P 7))
@@ -12699,7 +12699,7 @@
   else
      emit_insn (gen_cceq_ior_compare_complement (operands[9], andexpr, ctrcmpcc,
 						 operands[8], cccmp, ccin));
-  if (gpc_reg_operand (operands[0], <MODE>mode))
+  if (int_reg_operand (ctrout, <MODE>mode))
      emit_insn (gen_add<mode>3 (ctrout, ctr, constm1_rtx));
   else
     {