From: Wilco Dijkstra Date: Tue, 9 Sep 2025 10:30:39 +0000 (+0000) Subject: atomic: Switch power to builtin atomics X-Git-Tag: glibc-2.43~560 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b568af853b9f5a93544c8c49b6bd276474468504;p=thirdparty%2Fglibc.git atomic: Switch power to builtin atomics Switch power to builtin atomics. Reviewed-by: Adhemerval Zanella  --- diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h index f5624572d8..6f63c38e3d 100644 --- a/sysdeps/powerpc/atomic-machine.h +++ b/sysdeps/powerpc/atomic-machine.h @@ -25,16 +25,6 @@ * as appropriate and which in turn include this file. */ -/* - * Powerpc does not have byte and halfword forms of load and reserve and - * store conditional. So for powerpc we stub out the 8- and 16-bit forms. - */ -#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \ - (abort (), 0) - -#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \ - (abort (), 0) - #define __ARCH_ACQ_INSTR "isync" #ifndef __ARCH_REL_INSTR # define __ARCH_REL_INSTR "sync" @@ -48,269 +38,3 @@ #endif #define atomic_full_barrier() __asm ("sync" ::: "memory") - -#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __tmp; \ - __typeof (mem) __memp = (mem); \ - __asm __volatile ( \ - "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \ - " cmpw %0,%2\n" \ - " bne 2f\n" \ - " stwcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&r" (__tmp) \ - : "b" (__memp), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp; \ - }) - -#define __arch_compare_and_exchange_val_32_rel(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __tmp; \ - __typeof (mem) __memp = (mem); \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n" \ - " cmpw %0,%2\n" \ - " bne 2f\n" \ - " stwcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " \ - : "=&r" (__tmp) \ - : "b" (__memp), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp; \ - }) - -#define __arch_atomic_exchange_32_acq(mem, value) \ - ({ \ - __typeof (*mem) __val; \ - __asm __volatile ( \ - "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \ - " stwcx. %3,0,%2\n" \ - " bne- 1b\n" \ - " " __ARCH_ACQ_INSTR \ - : "=&r" (__val), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_32_rel(mem, value) \ - ({ \ - __typeof (*mem) __val; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n" \ - " stwcx. %3,0,%2\n" \ - " bne- 1b" \ - : "=&r" (__val), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_32(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile ("1: lwarx %0,0,%3\n" \ - " add %1,%0,%4\n" \ - " stwcx. %1,0,%3\n" \ - " bne- 1b" \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_32_acq(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile ("1: lwarx %0,0,%3" MUTEX_HINT_ACQ "\n" \ - " add %1,%0,%4\n" \ - " stwcx. %1,0,%3\n" \ - " bne- 1b\n" \ - __ARCH_ACQ_INSTR \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_32_rel(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: lwarx %0,0,%3" MUTEX_HINT_REL "\n" \ - " add %1,%0,%4\n" \ - " stwcx. %1,0,%3\n" \ - " bne- 1b" \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_increment_val_32(mem) \ - ({ \ - __typeof (*(mem)) __val; \ - __asm __volatile ("1: lwarx %0,0,%2\n" \ - " addi %0,%0,1\n" \ - " stwcx. %0,0,%2\n" \ - " bne- 1b" \ - : "=&b" (__val), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_decrement_val_32(mem) \ - ({ \ - __typeof (*(mem)) __val; \ - __asm __volatile ("1: lwarx %0,0,%2\n" \ - " subi %0,%0,1\n" \ - " stwcx. %0,0,%2\n" \ - " bne- 1b" \ - : "=&b" (__val), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_decrement_if_positive_32(mem) \ - ({ int __val, __tmp; \ - __asm __volatile ("1: lwarx %0,0,%3\n" \ - " cmpwi 0,%0,0\n" \ - " addi %1,%0,-1\n" \ - " ble 2f\n" \ - " stwcx. %1,0,%3\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_compare_and_exchange_val_32_acq(mem, newval, oldval); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_compare_and_exchange_val_64_acq(mem, newval, oldval); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_compare_and_exchange_val_32_rel(mem, newval, oldval); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_compare_and_exchange_val_64_rel(mem, newval, oldval); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_exchange_acq(mem, value) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_exchange_32_acq (mem, value); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_exchange_64_acq (mem, value); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_exchange_rel(mem, value) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_exchange_32_rel (mem, value); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_exchange_64_rel (mem, value); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_exchange_and_add(mem, value) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_exchange_and_add_32 (mem, value); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_exchange_and_add_64 (mem, value); \ - else \ - abort (); \ - __result; \ - }) -#define atomic_exchange_and_add_acq(mem, value) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_exchange_and_add_32_acq (mem, value); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_exchange_and_add_64_acq (mem, value); \ - else \ - abort (); \ - __result; \ - }) -#define atomic_exchange_and_add_rel(mem, value) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_exchange_and_add_32_rel (mem, value); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_exchange_and_add_64_rel (mem, value); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_increment_val(mem) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*(mem)) == 4) \ - __result = __arch_atomic_increment_val_32 (mem); \ - else if (sizeof (*(mem)) == 8) \ - __result = __arch_atomic_increment_val_64 (mem); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; }) - -#define atomic_decrement_val(mem) \ - ({ \ - __typeof (*(mem)) __result; \ - if (sizeof (*(mem)) == 4) \ - __result = __arch_atomic_decrement_val_32 (mem); \ - else if (sizeof (*(mem)) == 8) \ - __result = __arch_atomic_decrement_val_64 (mem); \ - else \ - abort (); \ - __result; \ - }) - -#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; }) - - -/* Decrement *MEM if it is > 0, and return the old value. */ -#define atomic_decrement_if_positive(mem) \ - ({ __typeof (*(mem)) __result; \ - if (sizeof (*mem) == 4) \ - __result = __arch_atomic_decrement_if_positive_32 (mem); \ - else if (sizeof (*mem) == 8) \ - __result = __arch_atomic_decrement_if_positive_64 (mem); \ - else \ - abort (); \ - __result; \ - }) diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h index 4534f30740..2e9860cb9d 100644 --- a/sysdeps/powerpc/powerpc32/atomic-machine.h +++ b/sysdeps/powerpc/powerpc32/atomic-machine.h @@ -33,67 +33,9 @@ #endif #define __HAVE_64B_ATOMICS 0 -#define USE_ATOMIC_COMPILER_BUILTINS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 1 #define ATOMIC_EXCHANGE_USES_CAS 1 -/* - * The 32-bit exchange_bool is different on powerpc64 because the subf - * does signed 64-bit arithmetic while the lwarx is 32-bit unsigned - * (a load word and zero (high 32) form). So powerpc64 has a slightly - * different version in sysdeps/powerpc/powerpc64/atomic-machine.h. - */ -#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \ -({ \ - unsigned int __tmp; \ - __asm __volatile ( \ - "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \ - " subf. %0,%2,%0\n" \ - " bne 2f\n" \ - " stwcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&r" (__tmp) \ - : "b" (mem), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp != 0; \ -}) - -/* Powerpc32 processors don't implement the 64-bit (doubleword) forms of - load and reserve (ldarx) and store conditional (stdcx.) instructions. - So for powerpc32 we stub out the 64-bit forms. */ -#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \ - (abort (), 0) - -#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ - (abort (), (__typeof (*mem)) 0) - -#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \ - (abort (), (__typeof (*mem)) 0) - -#define __arch_atomic_exchange_64_acq(mem, value) \ - ({ abort (); (*mem) = (value); }) - -#define __arch_atomic_exchange_64_rel(mem, value) \ - ({ abort (); (*mem) = (value); }) - -#define __arch_atomic_exchange_and_add_64(mem, value) \ - ({ abort (); (*mem) = (value); }) - -#define __arch_atomic_exchange_and_add_64_acq(mem, value) \ - ({ abort (); (*mem) = (value); }) - -#define __arch_atomic_exchange_and_add_64_rel(mem, value) \ - ({ abort (); (*mem) = (value); }) - -#define __arch_atomic_increment_val_64(mem) \ - ({ abort (); (*mem)++; }) - -#define __arch_atomic_decrement_val_64(mem) \ - ({ abort (); (*mem)--; }) - -#define __arch_atomic_decrement_if_positive_64(mem) \ - ({ abort (); (*mem)--; }) - #ifdef _ARCH_PWR4 /* * Newer powerpc64 processors support the new "light weight" sync (lwsync) diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h index 3754b55dda..9ae48a907d 100644 --- a/sysdeps/powerpc/powerpc64/atomic-machine.h +++ b/sysdeps/powerpc/powerpc64/atomic-machine.h @@ -33,195 +33,9 @@ #endif #define __HAVE_64B_ATOMICS 1 -#define USE_ATOMIC_COMPILER_BUILTINS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 1 #define ATOMIC_EXCHANGE_USES_CAS 1 -/* The 32-bit exchange_bool is different on powerpc64 because the subf - does signed 64-bit arithmetic while the lwarx is 32-bit unsigned - (a load word and zero (high 32) form) load. - In powerpc64 register values are 64-bit by default, including oldval. - The value in old val unknown sign extension, lwarx loads the 32-bit - value as unsigned. So we explicitly clear the high 32 bits in oldval. */ -#define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \ -({ \ - unsigned int __tmp, __tmp2; \ - __asm __volatile (" clrldi %1,%1,32\n" \ - "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n" \ - " subf. %0,%1,%0\n" \ - " bne 2f\n" \ - " stwcx. %4,0,%2\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&r" (__tmp), "=r" (__tmp2) \ - : "b" (mem), "1" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp != 0; \ -}) - -/* - * Only powerpc64 processors support Load doubleword and reserve index (ldarx) - * and Store doubleword conditional indexed (stdcx) instructions. So here - * we define the 64-bit forms. - */ -#define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \ -({ \ - unsigned long __tmp; \ - __asm __volatile ( \ - "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \ - " subf. %0,%2,%0\n" \ - " bne 2f\n" \ - " stdcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&r" (__tmp) \ - : "b" (mem), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp != 0; \ -}) - -#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __tmp; \ - __typeof (mem) __memp = (mem); \ - __asm __volatile ( \ - "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n" \ - " cmpd %0,%2\n" \ - " bne 2f\n" \ - " stdcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&r" (__tmp) \ - : "b" (__memp), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp; \ - }) - -#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \ - ({ \ - __typeof (*(mem)) __tmp; \ - __typeof (mem) __memp = (mem); \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: ldarx %0,0,%1" MUTEX_HINT_REL "\n" \ - " cmpd %0,%2\n" \ - " bne 2f\n" \ - " stdcx. %3,0,%1\n" \ - " bne- 1b\n" \ - "2: " \ - : "=&r" (__tmp) \ - : "b" (__memp), "r" (oldval), "r" (newval) \ - : "cr0", "memory"); \ - __tmp; \ - }) - -#define __arch_atomic_exchange_64_acq(mem, value) \ - ({ \ - __typeof (*mem) __val; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n" \ - " stdcx. %3,0,%2\n" \ - " bne- 1b\n" \ - " " __ARCH_ACQ_INSTR \ - : "=&r" (__val), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_64_rel(mem, value) \ - ({ \ - __typeof (*mem) __val; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: ldarx %0,0,%2" MUTEX_HINT_REL "\n" \ - " stdcx. %3,0,%2\n" \ - " bne- 1b" \ - : "=&r" (__val), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_64(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile ("1: ldarx %0,0,%3\n" \ - " add %1,%0,%4\n" \ - " stdcx. %1,0,%3\n" \ - " bne- 1b" \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_64_acq(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile ("1: ldarx %0,0,%3" MUTEX_HINT_ACQ "\n" \ - " add %1,%0,%4\n" \ - " stdcx. %1,0,%3\n" \ - " bne- 1b\n" \ - __ARCH_ACQ_INSTR \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_exchange_and_add_64_rel(mem, value) \ - ({ \ - __typeof (*mem) __val, __tmp; \ - __asm __volatile (__ARCH_REL_INSTR "\n" \ - "1: ldarx %0,0,%3" MUTEX_HINT_REL "\n" \ - " add %1,%0,%4\n" \ - " stdcx. %1,0,%3\n" \ - " bne- 1b" \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "r" (value), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_increment_val_64(mem) \ - ({ \ - __typeof (*(mem)) __val; \ - __asm __volatile ("1: ldarx %0,0,%2\n" \ - " addi %0,%0,1\n" \ - " stdcx. %0,0,%2\n" \ - " bne- 1b" \ - : "=&b" (__val), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_decrement_val_64(mem) \ - ({ \ - __typeof (*(mem)) __val; \ - __asm __volatile ("1: ldarx %0,0,%2\n" \ - " subi %0,%0,1\n" \ - " stdcx. %0,0,%2\n" \ - " bne- 1b" \ - : "=&b" (__val), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - -#define __arch_atomic_decrement_if_positive_64(mem) \ - ({ int __val, __tmp; \ - __asm __volatile ("1: ldarx %0,0,%3\n" \ - " cmpdi 0,%0,0\n" \ - " addi %1,%0,-1\n" \ - " ble 2f\n" \ - " stdcx. %1,0,%3\n" \ - " bne- 1b\n" \ - "2: " __ARCH_ACQ_INSTR \ - : "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \ - : "b" (mem), "m" (*mem) \ - : "cr0", "memory"); \ - __val; \ - }) - /* * All powerpc64 processors support the new "light weight" sync (lwsync). */