From: John David Anglin Date: Sun, 25 Jul 2004 21:19:28 +0000 (+0000) Subject: re PR target/15202 ([3.4 only] ICE in reload_cse_simplify_operands, at postreload.c) X-Git-Tag: releases/gcc-3.3.5~98 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b570c7b0218952f28c231be115679a3bc3852661;p=thirdparty%2Fgcc.git re PR target/15202 ([3.4 only] ICE in reload_cse_simplify_operands, at postreload.c) PR target/15202 * pa.md (movdi, movsi, movhi, movqi): Support move from shift amount register to general register for DI, SI, HI and QI modes. Remove move to shift amount register in DF mode. From-SVN: r85165 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e04dc1461dc..33c3a085d38c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2004-07-25 John David Anglin + PR target/15202 + * pa.md (movdi, movsi, movhi, movqi): Support move from shift amount + register to general register for DI, SI, HI and QI modes. Remove + move to shift amount register in DF mode. + PR rtl-optimization/14782 * pa.c (emit_move_sequence): Use SFmode for 4-byte modes when doing the address checks for secondary reloads for loads from and stores diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 4886b3ca06fd..1aace89b20c2 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -2264,9 +2264,9 @@ (define_insn "" [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" - "=r,r,r,r,r,r,Q,!*q,!f,f,*TR") + "=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR") (match_operand:SI 1 "move_operand" - "A,r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && ! TARGET_SOFT_FLOAT" @@ -2279,18 +2279,19 @@ ldw%M1 %1,%0 stw%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,sgl %f1,%0 fldw%F1 %1,%0 fstw%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" - "=r,r,r,r,r,r,Q,!*q") + "=r,r,r,r,r,r,Q,!*q,!r") (match_operand:SI 1 "move_operand" - "A,r,J,N,K,RQ,rM,!rM"))] + "A,r,J,N,K,RQ,rM,!rM,!*q"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)) && TARGET_SOFT_FLOAT" @@ -2302,10 +2303,11 @@ {zdepi|depwi,z} %Z1,%0 ldw%M1 %1,%0 stw%M0 %r1,%0 - mtsar %r1" - [(set_attr "type" "load,move,move,move,move,load,store,move") + mtsar %r1 + {mfctl|mfctl,w} %%sar,%0" + [(set_attr "type" "load,move,move,move,move,load,store,move,move") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2699,8 +2701,10 @@ }") (define_insn "" - [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,!*q,!*f") - (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,!rM,!*fM"))] + [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" + "=r,r,r,r,r,Q,!*q,!r,!*f") + (match_operand:HI 1 "move_operand" + "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] "register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode)" "@ @@ -2711,10 +2715,11 @@ ldh%M1 %1,%0 sth%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %sar,%0 fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu") + [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -2814,8 +2819,10 @@ }") (define_insn "" - [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,!*q,!*f") - (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,!rM,!*fM"))] + [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" + "=r,r,r,r,r,Q,!*q,!r,!*f") + (match_operand:QI 1 "move_operand" + "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))] "register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode)" "@ @@ -2826,10 +2833,11 @@ ldb%M1 %1,%0 stb%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,sgl %f1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu") + [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") @@ -3137,9 +3145,9 @@ (define_insn "" [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand" - "=r,r,r,r,r,Q,!*q,!f,f,*TR") + "=r,r,r,r,r,Q,!f,f,*TR") (match_operand:DF 1 "move_operand" - "r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))] + "r,J,N,K,RQ,rM,!fM,*RT,f"))] "(register_operand (operands[0], DFmode) || reg_or_0_operand (operands[1], DFmode)) && ! TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -3150,13 +3158,12 @@ depdi,z %z1,%0 ldd%M1 %1,%0 std%M0 %r1,%0 - mtsar %r1 fcpy,dbl %f1,%0 fldd%F1 %1,%0 fstd%F0 %1,%0" - [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:DF 0 "register_operand" "=fx") @@ -3296,9 +3303,9 @@ (define_insn "" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" - "=r,r,r,r,r,r,Q,!*q,!f,f,*TR") + "=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR") (match_operand:DI 1 "move_operand" - "A,r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))] + "A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))] "(register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode)) && ! TARGET_SOFT_FLOAT && TARGET_64BIT" @@ -3311,12 +3318,13 @@ ldd%M1 %1,%0 std%M0 %r1,%0 mtsar %r1 + {mfctl|mfctl,w} %%sar,%0 fcpy,dbl %f1,%0 fldd%F1 %1,%0 fstd%F0 %1,%0" - [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore") + [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore") (set_attr "pa_combine_type" "addmove") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")]) (define_insn "" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"