From: Georg-Johann Lay Date: Thu, 25 Jun 2026 11:23:19 +0000 (+0200) Subject: AVR: Fix GNU coding style. X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b57a95df0dbcd181fa36aae4fbfe5870e5b1524d;p=thirdparty%2Fbinutils-gdb.git AVR: Fix GNU coding style. This patch uses TABs for indentation in all places instead of blanks. gas/ * config/tc-avr.c: Fix indentations to follow GNU style. * config/tc-avr.h: Same. --- diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c index 819349a6fdd..35ca22693fe 100644 --- a/gas/config/tc-avr.c +++ b/gas/config/tc-avr.c @@ -46,12 +46,12 @@ struct avr_opcodes_s }; #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ -{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN}, + { #NAME, CONSTR, OPCODE, SIZE, ISA, BIN }, struct avr_opcodes_s avr_opcodes[] = { #include "opcode/avr.h" - {NULL, NULL, NULL, 0, 0, 0} + { NULL, NULL, NULL, 0, 0, 0 } }; @@ -64,7 +64,7 @@ struct avr_opcodes_s avr_opcodes[] = functions, however for small ISRs there might be some overhead. As implementing http://gcc.gnu.org/PR20296 would imply an almost complete - rewite of GCC's AVR back-end (which might pop up less optimized code in + rewrite of GCC's AVR back-end (which might pop up less optimized code in other places), we provide a pseudo-instruction which is resolved by GAS into ISR prologue / epilogue as expected by GCC. @@ -175,21 +175,21 @@ struct mcu_type_s static struct mcu_type_s mcu_types[] = { {"avr1", AVR_ISA_AVR1, bfd_mach_avr1}, -/* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2, - but set to AVR_ISA_AVR25 for some following version - of GCC (from 4.3) for backward compatibility. */ + /* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2, + but set to AVR_ISA_AVR25 for some following version + of GCC (from 4.3) for backward compatibility. */ {"avr2", AVR_ISA_AVR25, bfd_mach_avr2}, {"avr25", AVR_ISA_AVR25, bfd_mach_avr25}, -/* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3, - but set to AVR_ISA_AVR3_ALL for some following version - of GCC (from 4.3) for backward compatibility. */ + /* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3, + but set to AVR_ISA_AVR3_ALL for some following version + of GCC (from 4.3) for backward compatibility. */ {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3}, {"avr31", AVR_ISA_AVR31, bfd_mach_avr31}, {"avr35", AVR_ISA_AVR35, bfd_mach_avr35}, {"avr4", AVR_ISA_AVR4, bfd_mach_avr4}, -/* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5, - but set to AVR_ISA_AVR51 for some following version - of GCC (from 4.3) for backward compatibility. */ + /* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5, + but set to AVR_ISA_AVR51 for some following version + of GCC (from 4.3) for backward compatibility. */ {"avr5", AVR_ISA_AVR51, bfd_mach_avr5}, {"avr51", AVR_ISA_AVR51, bfd_mach_avr51}, {"avr6", AVR_ISA_AVR6, bfd_mach_avr6}, @@ -461,9 +461,9 @@ static struct mcu_type_s mcu_types[] = /* Current MCU type. */ -static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2}; -static struct mcu_type_s specified_mcu; -static struct mcu_type_s * avr_mcu = & default_mcu; +static struct mcu_type_s default_mcu = { "avr2", AVR_ISA_AVR2, bfd_mach_avr2 }; +static struct mcu_type_s specified_mcu; +static struct mcu_type_s *avr_mcu = & default_mcu; /* AVR target-specific switches. */ struct avr_opt_s @@ -472,8 +472,8 @@ struct avr_opt_s int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */ int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */ int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not) - relocations for linker relaxation. */ - int have_gccisr; /* Whether "__gcc_isr" is a known (pseudo) insn. */ + relocations for linker relaxation. */ + int have_gccisr; /* Whether "__gcc_isr" is a known (pseudo) insn. */ }; static struct avr_opt_s avr_opt = { 0, 0, 0, 0, 0 }; @@ -659,41 +659,42 @@ void md_show_usage (FILE *stream) { fprintf (stream, - _("AVR Assembler options:\n" - " -mmcu=[avr-name] select microcontroller variant\n" - " [avr-name] can be:\n" - " avr1 - classic AVR core without data RAM\n" - " avr2 - classic AVR core with up to 8K program memory\n" - " avr25 - classic AVR core with up to 8K program memory\n" - " plus the MOVW instruction\n" - " avr3 - classic AVR core with up to 64K program memory\n" - " avr31 - classic AVR core with up to 128K program memory\n" - " avr35 - classic AVR core with up to 64K program memory\n" - " plus the MOVW instruction\n" - " avr4 - enhanced AVR core with up to 8K program memory\n" - " avr5 - enhanced AVR core with up to 64K program memory\n" - " avr51 - enhanced AVR core with up to 128K program memory\n" - " avr6 - enhanced AVR core with up to 256K program memory\n" - " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n" - " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n" - " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" - " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" - " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n" - " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n" - " avrtiny - AVR Tiny core with 16 gp registers\n")); + _("AVR Assembler options:\n" + " -mmcu=[avr-name] select microcontroller variant\n" + " [avr-name] can be:\n" + " avr1 - classic AVR core without data RAM\n" + " avr2 - classic AVR core with up to 8K program memory\n" + " avr25 - classic AVR core with up to 8K program memory\n" + " plus the MOVW instruction\n" + " avr3 - classic AVR core with up to 64K program memory\n" + " avr31 - classic AVR core with up to 128K program memory\n" + " avr35 - classic AVR core with up to 64K program memory\n" + " plus the MOVW instruction\n" + " avr4 - enhanced AVR core with up to 8K program memory\n" + " avr5 - enhanced AVR core with up to 64K program memory\n" + " avr51 - enhanced AVR core with up to 128K program memory\n" + " avr6 - enhanced AVR core with up to 256K program memory\n" + " avrxmega2 - XMEGA, > 8K, <= 64K FLASH, < 64K RAM\n" + " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n" + " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" + " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" + " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n" + " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n" + " avrtiny - AVR Reduced core with 16 gp registers\n" + )); fprintf (stream, - _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" - " -mno-skip-bug disable warnings for skipping two-word instructions\n" - " (default for avr4, avr5)\n" - " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n" - " (default for avr3, avr5)\n" - " -mrmw accept Read-Modify-Write instructions\n" - " -mlink-relax generate relocations for linker relaxation (default)\n" - " -mno-link-relax don't generate relocations for linker relaxation.\n" - " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n" - " -mno-dollar-line-separator\n" - " do not treat the $ character as a line separator.\n" - )); + _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" + " -mno-skip-bug disable warnings for skipping two-word instructions\n" + " (default for avr4, avr5)\n" + " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n" + " (default for avr3, avr5)\n" + " -mrmw accept Read-Modify-Write instructions\n" + " -mlink-relax generate relocations for linker relaxation (default)\n" + " -mno-link-relax don't generate relocations for linker relaxation.\n" + " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n" + " -mno-dollar-line-separator\n" + " do not treat the $ character as a line separator.\n" + )); show_mcu_list (stream); } @@ -727,7 +728,7 @@ md_parse_option (int c, const char *arg) } /* It is OK to redefine mcu type within the same avr[1-5] bfd machine - type - this for allows passing -mmcu=... via gcc ASM_SPEC as well + type - this allows for passing -mmcu=... via gcc ASM_SPEC as well as .arch ... in the asm output at the same time. */ if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach) { @@ -951,8 +952,8 @@ avr_ldi_expression (expressionS *exp) ++str; if (startswith (str, "pm(") - || startswith (str, "gs(") - || startswith (str, "-(gs(") + || startswith (str, "gs(") + || startswith (str, "-(gs(") || startswith (str, "-(pm(")) { if (HAVE_PM_P (mod)) @@ -963,8 +964,8 @@ avr_ldi_expression (expressionS *exp) else as_bad (_("illegal expression")); - if (str[0] == 'g' || str[2] == 'g') - linker_stubs_should_be_generated = 1; + if (str[0] == 'g' || str[2] == 'g') + linker_stubs_should_be_generated = 1; if (*str == '-') { @@ -1059,56 +1060,56 @@ avr_operand (struct avr_opcodes_s *opcode, case 'a': case 'v': { - char * old_str = str; - char *lower; - char r_name[20]; + char * old_str = str; + char *lower; + char r_name[20]; - str = extract_word (str, r_name, sizeof (r_name)); - for (lower = r_name; *lower; ++lower) + str = extract_word (str, r_name, sizeof (r_name)); + for (lower = r_name; *lower; ++lower) { if (*lower >= 'A' && *lower <= 'Z') *lower += 'a' - 'A'; - } + } - if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0) - /* Single-digit register number, ie r0-r9. */ - op_mask = r_name[1] - '0'; - else if (r_name[0] == 'r' && ISDIGIT (r_name[1]) + if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0) + // Single-digit register number, ie r0-r9. + op_mask = r_name[1] - '0'; + else if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && ISDIGIT (r_name[2]) && r_name[3] == 0) - /* Double-digit register number, ie r10 - r32. */ - op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0'; - else if (r_name[0] >= 'x' && r_name[0] <= 'z' + // Double-digit register number, ie r10 - r32. + op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0'; + else if (r_name[0] >= 'x' && r_name[0] <= 'z' && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0) - /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */ - op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26; - else if ((*op == 'v' || *op == 'w') + // Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. + op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26; + else if ((*op == 'v' || *op == 'w') && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0) - /* For the movw and addiw instructions, refer to registers x, y and z by name. */ - op_mask = (r_name[0] - 'x') * 2 + 26; - else - { - /* Numeric or symbolic constant register number. */ - op_mask = avr_get_constant (old_str, 31); - str = input_line_pointer; - } + // For movw and addiw, refer to registers x, y and z by name. + op_mask = (r_name[0] - 'x') * 2 + 26; + else + { + /* Numeric or symbolic constant register number. */ + op_mask = avr_get_constant (old_str, 31); + str = input_line_pointer; + } } if (pregno) *pregno = op_mask; if (avr_mcu->mach == bfd_mach_avrtiny) - { - if (op_mask < 16 || op_mask > 31) - { - as_bad (_("register name or number from 16 to 31 required")); - break; - } - } + { + if (op_mask < 16 || op_mask > 31) + { + as_bad (_("register name or number from 16 to 31 required")); + break; + } + } else if (op_mask > 31) - { - as_bad (_("register name or number from 0 to 31 required")); - break; - } + { + as_bad (_("register name or number from 0 to 31 required")); + break; + } switch (*op) { @@ -1184,12 +1185,12 @@ avr_operand (struct avr_opcodes_s *opcode, if (*str == '+') { ++str; - const char *s; - for (s = opcode->opcode; *s; ++s) - { - if (*s == '+') - op_mask |= (1 << (15 - (s - opcode->opcode))); - } + const char *s; + for (s = opcode->opcode; *s; ++s) + { + if (*s == '+') + op_mask |= (1 << (15 - (s - opcode->opcode))); + } } /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */ @@ -1418,8 +1419,8 @@ avr_operands (struct avr_opcodes_s *opcode, char **line) { /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs (AVR core bug, fixed in the newer devices). */ - if (!(avr_opt.no_skip_bug || - (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW))) + if (!(avr_opt.no_skip_bug + || (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW))) && AVR_SKIP_P (frag_now->tc_frag_data.prev_opcode)) as_warn (_("skipping two-word instruction")); @@ -1464,8 +1465,8 @@ static bool relaxable_section (asection *sec) { return ((sec->flags & SEC_DEBUGGING) == 0 - && (sec->flags & SEC_CODE) != 0 - && (sec->flags & SEC_ALLOC) != 0); + && (sec->flags & SEC_CODE) != 0 + && (sec->flags & SEC_ALLOC) != 0); } /* Does whatever the xtensa port does. */ @@ -1486,8 +1487,8 @@ avr_validate_fix_sub (fixS *fix) fix is not valid. If the segment is not "relaxable", then the fix should have been handled earlier. */ add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); - if (! SEG_NORMAL (add_symbol_segment) || - ! relaxable_section (add_symbol_segment)) + if (! SEG_NORMAL (add_symbol_segment) + || ! relaxable_section (add_symbol_segment)) return 0; sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); @@ -1535,33 +1536,33 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) else if (linkrelax && fixP->fx_subsy) { /* For a subtraction relocation expression, generate one - of the DIFF relocs, with the value being the difference. - Note that a sym1 - sym2 expression is adjusted into a - section_start_sym + sym4_offset_from_section_start - sym1 - expression. fixP->fx_addsy holds the section start symbol, - fixP->fx_offset holds sym2's offset, and fixP->fx_subsy - holds sym1. Calculate the current difference and write value, - but leave fx_offset as is - during relaxation, - fx_offset - value gives sym1's value. */ + of the DIFF relocs, with the value being the difference. + Note that a sym1 - sym2 expression is adjusted into a + section_start_sym + sym4_offset_from_section_start - sym1 + expression. fixP->fx_addsy holds the section start symbol, + fixP->fx_offset holds sym2's offset, and fixP->fx_subsy + holds sym1. Calculate the current difference and write value, + but leave fx_offset as is - during relaxation, + fx_offset - value gives sym1's value. */ switch (fixP->fx_r_type) - { - case BFD_RELOC_8: - fixP->fx_r_type = BFD_RELOC_AVR_DIFF8; - break; - case BFD_RELOC_16: - fixP->fx_r_type = BFD_RELOC_AVR_DIFF16; - break; - case BFD_RELOC_32: - fixP->fx_r_type = BFD_RELOC_AVR_DIFF32; - break; - default: - as_bad_subtract (fixP); - break; - } + { + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_AVR_DIFF8; + break; + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_AVR_DIFF16; + break; + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_AVR_DIFF32; + break; + default: + as_bad_subtract (fixP); + break; + } value = S_GET_VALUE (fixP->fx_addsy) + - fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy); + fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy); *valP = value; fixP->fx_subsy = NULL; @@ -1586,7 +1587,7 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) break; case BFD_RELOC_AVR_DIFF8: *where = value; - break; + break; case BFD_RELOC_AVR_DIFF16: bfd_putl16 (value, where); break; @@ -1652,10 +1653,10 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) break; case BFD_RELOC_8: - if (value > 255 || value < -128) + if (value > 255 || value < -128) as_warn_where (fixP->fx_file, fixP->fx_line, _("operand out of range: %ld"), value); - *where = value; + *where = value; break; case BFD_RELOC_AVR_16_PM: @@ -1764,19 +1765,19 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) } break; - case BFD_RELOC_AVR_8_LO: - *where = 0xff & value; - break; + case BFD_RELOC_AVR_8_LO: + *where = 0xff & value; + break; - case BFD_RELOC_AVR_8_HI: - *where = 0xff & (value >> 8); - break; + case BFD_RELOC_AVR_8_HI: + *where = 0xff & (value >> 8); + break; - case BFD_RELOC_AVR_8_HLO: - *where = 0xff & (value >> 16); - break; + case BFD_RELOC_AVR_8_HLO: + *where = 0xff & (value >> 16); + break; - default: + default: as_fatal (_("line %d: unknown relocation type: 0x%x"), fixP->fx_line, fixP->fx_r_type); break; @@ -1868,7 +1869,6 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) reloc->address = fixp->fx_offset; - return reloc; } @@ -1888,23 +1888,23 @@ md_assemble (char *str) if (opcode && !avr_opt.all_opcodes) { /* Check if the instruction's ISA bit is ON in the ISA bits of the part - specified by the user. If not look for other instructions + specified by the user. If not look for other instructions specifications with same mnemonic who's ISA bits matches. - This requires include/opcode/avr.h to have the instructions with - same mnemonic to be specified in sequence. */ + This requires include/opcode/avr.h to have the instructions with + same mnemonic to be specified in sequence. */ while ((opcode->isa & avr_mcu->isa) != opcode->isa) - { - opcode++; - - if (opcode->name && strcmp(op, opcode->name)) - { - as_bad (_("illegal opcode `%s' for mcu %s"), - (opcode - 1)->name, avr_mcu->name); - return; - } - } + { + opcode++; + + if (opcode->name && strcmp(op, opcode->name)) + { + as_bad (_("illegal opcode `%s' for mcu %s"), + (opcode - 1)->name, avr_mcu->name); + return; + } + } } if (opcode == NULL) @@ -2006,7 +2006,7 @@ avr_parse_cons_expression (expressionS *exp, int nbytes) input_line_pointer = tmp; - break; + break; } } @@ -2337,7 +2337,7 @@ create_record_for_frag (segT sec, fragS *fragP) static struct avr_property_record_link ** append_records_for_section (segT sec, - struct avr_property_record_link **next_ptr) + struct avr_property_record_link **next_ptr) { segment_info_type *seginfo = seg_info (sec); fragS *fragP; @@ -2345,19 +2345,19 @@ append_records_for_section (segT sec, if (seginfo && seginfo->frchainP) { for (fragP = seginfo->frchainP->frch_root; - fragP; - fragP = fragP->fr_next) + fragP; + fragP = fragP->fr_next) { - if (fragP->tc_frag_data.is_align - || fragP->tc_frag_data.is_org) - { - /* Create a single new entry. */ - struct avr_property_record_link *new_link - = create_record_for_frag (sec, fragP); - - *next_ptr = new_link; - next_ptr = &new_link->next; - } + if (fragP->tc_frag_data.is_align + || fragP->tc_frag_data.is_org) + { + /* Create a single new entry. */ + struct avr_property_record_link *new_link + = create_record_for_frag (sec, fragP); + + *next_ptr = new_link; + next_ptr = &new_link->next; + } } } @@ -2884,8 +2884,8 @@ avr_pre_output_hook (void) bfd_map_over_sections (stdoutput, avr_check_gccisr_done, NULL); } -/* Return false if the fixup in fixp should be left alone and not - adjusted. */ + +/* Return false if the fixup in fixp should be left alone and not adjusted. */ bool avr_fix_adjustable (struct fix *fixp) diff --git a/gas/config/tc-avr.h b/gas/config/tc-avr.h index 14877e97e4a..d047546c393 100644 --- a/gas/config/tc-avr.h +++ b/gas/config/tc-avr.h @@ -116,13 +116,14 @@ extern void avr_cons_fix_new (fragS *,int, int, expressionS *, /* If defined, this macro allows control over whether fixups for a given section will be processed when the linkrelax variable is - set. Define it to zero and handle things in md_apply_fix instead.*/ + set. Define it to zero and handle things in md_apply_fix instead. */ #define TC_LINKRELAX_FIXUP(SEG) 0 -/* If this macro returns non-zero, it guarantees that a relocation will be emitted - even when the value can be resolved locally. Do that if linkrelax is turned on */ +/* If this macro returns non-zero, it guarantees that a relocation will + be emitted even when the value can be resolved locally. Do that if + linkrelax is turned on. */ #define TC_FORCE_RELOCATION(fix) avr_force_relocation (fix) -#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \ +#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \ (GENERIC_FORCE_RELOCATION_SUB_SAME (fix, seg) \ || avr_force_relocation (fix)) extern int avr_force_relocation (struct fix *); @@ -161,21 +162,21 @@ extern int avr_force_relocation (struct fix *); However, there is no serious performance penalty when making the linker make the fixup work. Check also that fx_addsy is not NULL, in order to make sure that the fixup refers to some sort of label. */ -#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \ - if ( (FIXP->fx_r_type == BFD_RELOC_AVR_7_PCREL \ - || FIXP->fx_r_type == BFD_RELOC_AVR_13_PCREL \ - || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM \ - || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_GS \ - || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM \ - || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_GS \ - || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM \ +#define TC_VALIDATE_FIX(FIXP,SEG,SKIP) \ + if ((FIXP->fx_r_type == BFD_RELOC_AVR_7_PCREL \ + || FIXP->fx_r_type == BFD_RELOC_AVR_13_PCREL \ + || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM \ + || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_GS \ + || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM \ + || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_GS \ + || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM \ || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM_NEG \ || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM_NEG \ || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM_NEG \ - || FIXP->fx_r_type == BFD_RELOC_AVR_8_LO \ - || FIXP->fx_r_type == BFD_RELOC_AVR_8_HI \ - || FIXP->fx_r_type == BFD_RELOC_AVR_8_HLO \ - || FIXP->fx_r_type == BFD_RELOC_AVR_16_PM) \ + || FIXP->fx_r_type == BFD_RELOC_AVR_8_LO \ + || FIXP->fx_r_type == BFD_RELOC_AVR_8_HI \ + || FIXP->fx_r_type == BFD_RELOC_AVR_8_HLO \ + || FIXP->fx_r_type == BFD_RELOC_AVR_16_PM) \ && FIXP->fx_addsy != NULL \ && FIXP->fx_subsy == NULL) \ { \