From: Vineet Gupta Date: Fri, 4 Jul 2025 19:33:09 +0000 (-0700) Subject: RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b5d0cfab39608ff1f010a571122d6105b6e0e91e;p=thirdparty%2Fgcc.git RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 Spotted this by chance as I saw a similar fixup in comment. From comments, I think this is needed, but I've not hit any issues due to this. gcc/ChangeLog: * config/riscv/predicates.md (prefetch_operand): mack 5 bits. Signed-off-by: Vineet Gupta (cherry picked from commit b960201091fcab631a34a8c8d5b30e9f297dfbe5) --- diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index c20d82c5516..715ac962032 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -33,11 +33,11 @@ (define_predicate "prefetch_operand" (ior (match_operand 0 "register_operand") (and (match_test "const_arith_operand (op, VOIDmode)") - (match_test "(INTVAL (op) & 0xf) == 0")) + (match_test "(INTVAL (op) & 0x1f) == 0")) (and (match_code "plus") (match_test "register_operand (XEXP (op, 0), word_mode)") (match_test "const_arith_operand (XEXP (op, 1), VOIDmode)") - (match_test "(INTVAL (XEXP (op, 1)) & 0xf) == 0")))) + (match_test "(INTVAL (XEXP (op, 1)) & 0x1f) == 0")))) (define_predicate "lui_operand" (and (match_code "const_int")