From: VMware, Inc <>
Date: Wed, 24 Feb 2010 21:12:42 +0000 (-0800)
Subject: Changes in shared code that don't affect open-vm-tools functionality.
X-Git-Tag: 2010.02.23-236320~53
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b5ffb4cb7e42c16ffde077f6f9ce990b21bd2234;p=thirdparty%2Fopen-vm-tools.git

Changes in shared code that don't affect open-vm-tools functionality.

Signed-off-by: Marcelo Vanzin <mvanzin@vmware.com>
---

diff --git a/open-vm-tools/lib/include/vm_atomic.h b/open-vm-tools/lib/include/vm_atomic.h
index 82d22ef8f..342ac1423 100644
--- a/open-vm-tools/lib/include/vm_atomic.h
+++ b/open-vm-tools/lib/include/vm_atomic.h
@@ -617,45 +617,6 @@ Atomic_And(Atomic_uint32 *var, // IN
 #define Atomic_And32 Atomic_And
 
 
-#if defined(__x86_64__)
-/*
- *-----------------------------------------------------------------------------
- *
- * Atomic_And64 --
- *
- *      Atomic read, bitwise AND with a value, write.
- *
- * Results:
- *      None
- *
- * Side effects:
- *      None
- *
- *-----------------------------------------------------------------------------
- */
-
-static INLINE void
-Atomic_And64(Atomic_uint64 *var, // IN
-             uint64 val)         // IN
-{
-#if defined(__GNUC__)
-   /* Checked against the AMD manual and GCC --hpreg */
-   __asm__ __volatile__(
-      "lock; andq %1, %0"
-      : "+m" (var->value)
-      : "ri" (val)
-      : "cc"
-   );
-   AtomicEpilogue();
-#elif defined _MSC_VER
-   _InterlockedAnd64((__int64 *)&var->value, (__int64)val);
-#else
-#error No compiler defined for Atomic_And64
-#endif
-}
-#endif
-
-
 /*
  *-----------------------------------------------------------------------------
  *
@@ -718,45 +679,6 @@ Atomic_Or(Atomic_uint32 *var, // IN
 #define Atomic_Or32 Atomic_Or
 
 
-#if defined(__x86_64__)
-/*
- *-----------------------------------------------------------------------------
- *
- * Atomic_Or64 --
- *
- *      Atomic read, bitwise OR with a value, write.
- *
- * Results:
- *      None
- *
- * Side effects:
- *      None
- *
- *-----------------------------------------------------------------------------
- */
-
-static INLINE void
-Atomic_Or64(Atomic_uint64 *var, // IN
-            uint64 val)         // IN
-{
-#if defined(__GNUC__)
-   /* Checked against the AMD manual and GCC --hpreg */
-   __asm__ __volatile__(
-      "lock; orq %1, %0"
-      : "+m" (var->value)
-      : "ri" (val)
-      : "cc"
-   );
-   AtomicEpilogue();
-#elif defined _MSC_VER
-   _InterlockedOr64((__int64 *)&var->value, (__int64)val);
-#else
-#error No compiler defined for Atomic_Or64
-#endif
-}
-#endif
-
-
 /*
  *-----------------------------------------------------------------------------
  *
@@ -1792,6 +1714,8 @@ Atomic_CMPXCHG32(Atomic_uint32 *var,   // IN/OUT
 #define Atomic_Dec64(x)           _fnAtomic_Dec64_NotImplementedOnARM
 #define Atomic_ReadWrite64(x,y)   _fnAtomic_ReadWrite64_NotImplementedOnARM
 #define Atomic_Write64(x,y)       _fnAtomic_Write64_NotImplementedOnARM
+#define Atomic_And64(x)           _fnAtomic_And64_NotImplementedOnARM
+#define Atomic_Or64(x)            _fnAtomic_Or64_NotImplementedOnARM
 
 #else // __arm__
 
@@ -2092,6 +2016,99 @@ Atomic_Write64(Atomic_uint64 *var, // IN
    (void)Atomic_ReadWrite64(var, val);
 #endif
 }
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * Atomic_Or64 --
+ *
+ *      Atomic read, bitwise OR with a 64-bit value, write.
+ *
+ * Results:
+ *      None
+ *
+ * Side effects:
+ *      None
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+static INLINE void
+Atomic_Or64(Atomic_uint64 *var, // IN
+            uint64 val)         // IN
+{
+#if defined(__x86_64__)
+#if defined(__GNUC__)
+   /* Checked against the AMD manual and GCC --hpreg */
+   __asm__ __volatile__(
+      "lock; orq %1, %0"
+      : "+m" (var->value)
+      : "ri" (val)
+      : "cc"
+   );
+   AtomicEpilogue();
+#elif defined _MSC_VER
+   _InterlockedOr64((__int64 *)&var->value, (__int64)val);
+#else
+#error No compiler defined for Atomic_Or64
+#endif
+#else // __x86_64__
+   uint64 oldVal;
+   uint64 newVal;
+   do {
+      oldVal = var->value;
+      newVal = oldVal | val;
+   } while (!Atomic_CMPXCHG64(var, &oldVal, &newVal));
+#endif
+}
+
+
+/*
+ *-----------------------------------------------------------------------------
+ *
+ * Atomic_And64 --
+ *
+ *      Atomic read, bitwise AND with a 64-bit value, write.
+ *
+ * Results:
+ *      None
+ *
+ * Side effects:
+ *      None
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+static INLINE void
+Atomic_And64(Atomic_uint64 *var, // IN
+             uint64 val)         // IN
+{
+#if defined(__x86_64__)
+#if defined(__GNUC__)
+   /* Checked against the AMD manual and GCC --hpreg */
+   __asm__ __volatile__(
+      "lock; andq %1, %0"
+      : "+m" (var->value)
+      : "ri" (val)
+      : "cc"
+   );
+   AtomicEpilogue();
+#elif defined _MSC_VER
+   _InterlockedAnd64((__int64 *)&var->value, (__int64)val);
+#else
+#error No compiler defined for Atomic_And64
+#endif
+#else // __x86_64__
+   uint64 oldVal;
+   uint64 newVal;
+   do {
+      oldVal = var->value;
+      newVal = oldVal & val;
+   } while (!Atomic_CMPXCHG64(var, &oldVal, &newVal));
+#endif
+}
+
 #endif // __arm__