From: Juzhe-Zhong Date: Wed, 31 May 2023 10:43:44 +0000 (+0800) Subject: RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to float widening conversion) X-Git-Tag: basepoints/gcc-15~8700 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b65458005dfb38f2efdca52e42f3dbf4760f91bd;p=thirdparty%2Fgcc.git RISC-V: Remove FRM for vfwcvt.f.x.v (RVV integer to float widening conversion) Base on the discussion here: https://github.com/riscv/riscv-v-spec/issues/884 vfwcvt.f.x.v doesn't depend on FRM. So remove FRM preparing for mode switching support. gcc/ChangeLog: * config/riscv/vector.md: Remove FRM. Signed-off-by: Pan Li --- diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 60f052bcec92..cb4e77e7854b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7159,10 +7159,8 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF (match_operand: 3 "register_operand" " vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0")))]