From: Kwok Cheung Yeung <kcy@codesourcery.com>
Date: Tue, 27 Sep 2022 21:24:55 +0000 (+0000)
Subject: amdgcn: Fix instruction generation for exp2 and log2 operations
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b656c03ff8c4803e3af13429e2bec93709946f2f;p=thirdparty%2Fgcc.git

amdgcn: Fix instruction generation for exp2 and log2 operations

The GCN instructions for the exp2 and log2 operations are v_exp_* and v_log_*
respectively, which unfortunately do not line up with the RTL naming
convention.  To deal with this, a new set of int attributes is now used when
generating the assembly for these instructions.

2022-09-27  Kwok Cheung Yeung  <kcy@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (math_unop_insn): New attribute.
	(<math_unop><mode>2, <math_unop><mode>2<exec>, <math_unop><mode>2,
	<math_unop><mode>2<exec>, *<math_unop><mode>2_insn,
	*<math_unop><mode>2<exec>_insn): Use math_unop_insn to generate
	assembler output.
---

diff --git a/gcc/ChangeLog.omp b/gcc/ChangeLog.omp
index ed2073297e7c..39e094476c9a 100644
--- a/gcc/ChangeLog.omp
+++ b/gcc/ChangeLog.omp
@@ -1,3 +1,11 @@
+2022-09-27  Kwok Cheung Yeung  <kcy@codesourcery.com>
+
+	* config/gcn/gcn-valu.md (math_unop_insn): New attribute.
+	(<math_unop><mode>2, <math_unop><mode>2<exec>, <math_unop><mode>2,
+	<math_unop><mode>2<exec>, *<math_unop><mode>2_insn,
+	*<math_unop><mode>2<exec>_insn): Use math_unop_insn to generate
+	assembler output.
+
 2022-09-26  Thomas Schwinge  <thomas@codesourcery.com>
 
 	Backported from master:
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 5c66f4f680ba..838ce84dacb5 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2312,13 +2312,21 @@
    (UNSPEC_SIN "sin")
    (UNSPEC_COS "cos")])
 
+(define_int_attr math_unop_insn
+  [(UNSPEC_FLOOR "floor")
+   (UNSPEC_CEIL "ceil")
+   (UNSPEC_EXP2 "exp")
+   (UNSPEC_LOG2 "log")
+   (UNSPEC_SIN "sin")
+   (UNSPEC_COS "cos")])
+
 (define_insn "<math_unop><mode>2"
   [(set (match_operand:FP 0 "register_operand"  "=  v")
 	(unspec:FP
 	  [(match_operand:FP 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_1OR2REG))]
   ""
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])
 
@@ -2328,7 +2336,7 @@
 	  [(match_operand:V_FP 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_1OR2REG))]
   ""
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])
 
@@ -2338,7 +2346,7 @@
 	  [(match_operand:FP_1REG 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_1REG))]
   "flag_unsafe_math_optimizations"
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])
 
@@ -2348,7 +2356,7 @@
 	  [(match_operand:V_FP_1REG 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_1REG))]
   "flag_unsafe_math_optimizations"
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])
 
@@ -2358,7 +2366,7 @@
 	  [(match_operand:FP_1REG 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_TRIG))]
   "flag_unsafe_math_optimizations"
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])
 
@@ -2368,7 +2376,7 @@
 	  [(match_operand:V_FP_1REG 1 "gcn_alu_operand" "vSvB")]
 	  MATH_UNOP_TRIG))]
   "flag_unsafe_math_optimizations"
-  "v_<math_unop>%i0\t%0, %1"
+  "v_<math_unop_insn>%i0\t%0, %1"
   [(set_attr "type" "vop1")
    (set_attr "length" "8")])