From: Marek Pikuła Date: Thu, 27 Mar 2025 14:09:14 +0000 (+0100) Subject: doc/riscv: Add description of disassembler options X-Git-Tag: binutils-2_45~1038 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b667765b2c3e098c5930c28c2f89584523bf99d6;p=thirdparty%2Fbinutils-gdb.git doc/riscv: Add description of disassembler options Up to this point, no mention of RISC-V-specific disassembler options was mentioned in binutils documentation. This patch includes description for all of the currently supported options. Signed-off-by: Marek Pikuła --- diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi index 73848e3b390..5bf5d80b85b 100644 --- a/binutils/doc/binutils.texi +++ b/binutils/doc/binutils.texi @@ -2701,6 +2701,23 @@ If you disassemble without giving a CPU selection, a default will be chosen from information gleaned by BFD from the object files headers, but the result again may not be as you expect. +For RISC-V, the following options are supported: + +@table @code +@item numeric +Print numeric register names, rather than ABI names (e.g., print @code{x2} +instead of @code{sp}). + +@item no-aliases +Disassemble only into canonical instructions. For example, compressed +instructions will be represented as such (@code{addi sp,sp,-128} will be +@code{c.addi16sp sp,-128}). + +@item priv-spec=@var{SPEC} +Print the CSR according to the chosen privilege spec version (e.g., +@code{1.10}, @code{1.11}, @code{1.12}). +@end table + For MIPS, this option controls the printing of instruction mnemonic names and register names in disassembled instructions. Multiple selections from the following may be specified as a comma separated