From: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Date: Thu, 15 Jan 2026 16:49:05 +0000 (+0100)
Subject: ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b686ccad06a8c3b041e89e19e52d7b1ba5dd93f7;p=thirdparty%2Fkernel%2Flinux.git

ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling

In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the
'ref' clock frequency value is set to 500 MHz which is the default 'ref'
clock frequency value.

Add support for CPU frequency scaling defining those 3 frequencies in
the opp-table with the assumption that the 'ref' clock is set to its
default value.

Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260115164905.1203453-1-herve.codina@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index f4f760aff28bd..0c6d6d8343954 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -15,6 +15,39 @@
 	#size-cells = <1>;
 	interrupt-parent = <&gic>;
 
+	/*
+	 * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor)
+	 * with x1, x2 or x4 ratio between the CPUs clock frequency and this
+	 * 'ref' clock frequency.
+	 *
+	 * The table below is built on the assumption that the 'ref' clock
+	 * frequency is set to 500MHz which is its default value.
+	 *
+	 * The table should be overridden in the board device-tree file based
+	 * on the 'ref' clock frequency if this frequency value is not the
+	 * default one.
+	 */
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-125000000 {
+			opp-hz = /bits/ 64 <125000000>;
+			/* ~35 clocks cycles at 125mhz */
+			clock-latency-ns = <300>;
+		};
+
+		opp-250000000 {
+			opp-hz = /bits/ 64 <250000000>;
+			clock-latency-ns = <300>;
+		};
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			clock-latency-ns = <300>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -24,6 +57,7 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		cpu@1 {
@@ -33,6 +67,7 @@
 			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
 			enable-method = "renesas,r9a06g032-smp";
 			cpu-release-addr = <0 0x4000c204>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 	};