From: Julian Seward Date: Wed, 4 Jun 2014 11:36:54 +0000 (+0000) Subject: Support movi_{16b,8b}_#imm8. Fixes #335262. (dimitry@google.com) X-Git-Tag: svn/VALGRIND_3_10_1^2~104 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b7d69bfb32cb3528293553c11eb01e665681684a;p=thirdparty%2Fvalgrind.git Support movi_{16b,8b}_#imm8. Fixes #335262. (dimitry@google.com) git-svn-id: svn://svn.valgrind.org/vex/trunk@2866 --- diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 25659b85c8..7876ee11ed 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -5398,7 +5398,7 @@ Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn) MOV Vd.2d #imm (q=1) Allowable op:cmode FMOV = 1:1111 - MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, 11110 + MOVI = 0:xx00, 1:0x00, 1:10x0, 1:110x, x:1110 */ if (INSN(31,31) == 0 && INSN(28,19) == BITS10(0,1,1,1,1,0,0,0,0,0) @@ -5418,7 +5418,7 @@ Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn) case BITS5(1,0,0,0,0): case BITS5(1,0,1,0,0): // 1:0x00 case BITS5(1,1,0,0,0): case BITS5(1,1,0,1,0): // 1:10x0 case BITS5(1,1,1,0,0): case BITS5(1,1,1,0,1): // 1:110x - case BITS5(1,1,1,1,0): // 1:1110 + case BITS5(1,1,1,1,0): case BITS5(0,1,1,1,0): // x:1110 ok = True; break; default: break;