From: Daehwan Jung Date: Mon, 10 Jun 2024 11:39:11 +0000 (+0900) Subject: usb: dwc3: Support quirk for writing high-low order X-Git-Tag: v6.11-rc1~102^2~70 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b7ec7fd63256ff39eb95e27546efbd16b3915bf4;p=thirdparty%2Fkernel%2Flinux.git usb: dwc3: Support quirk for writing high-low order There's the limitation of Synopsys dwc3 controller with ERST programming in supporting separate ERSTBA_HI and ERSTBA_LO programming. It's supported when the ERSTBA is programmed ERSTBA_HI before ERSTBA_LO. But, writing operations in xHCI is done low-high order following xHCI spec. xHCI specification 5.1 "Register Conventions" states that 64 bit registers should be written in low-high order. Synopsys dwc3 needs workaround for high-low order. That's why adding new quirk is needed to support this. Signed-off-by: Daehwan Jung Link: https://lore.kernel.org/r/1718019553-111939-2-git-send-email-dh10.jung@samsung.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index a171b27a7845a..e0533cee6870b 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -126,7 +126,7 @@ out: int dwc3_host_init(struct dwc3 *dwc) { - struct property_entry props[5]; + struct property_entry props[6]; struct platform_device *xhci; int ret, irq; int prop_idx = 0; @@ -162,6 +162,8 @@ int dwc3_host_init(struct dwc3 *dwc) props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk"); + props[prop_idx++] = PROPERTY_ENTRY_BOOL("write-64-hi-lo-quirk"); + if (dwc->usb3_lpm_capable) props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");