From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Mon, 7 Nov 2016 20:54:42 +0000 (+0100)
Subject: rs6000: Do swdiv at expand time
X-Git-Tag: basepoints/gcc-8~3324
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b7fa8414c43a7b5f2971753473f550af94481ff3;p=thirdparty%2Fgcc.git

rs6000: Do swdiv at expand time

We transform floating point divide instructions to a faster series of
simple instructions, "swdiv".  Currently we do not do that until the
first splitter pass, which is much too late for most optimisations
that can happen on those new instructions, e.g. the constant loads
are not CSEd inside an unrolled loop.  This patch changes things so
those divide instructions are expanded during expand already.


	* config/rs6000/rs6000.md (div<mode>3): Expand using rs6000_emit_swdiv
	if appropriate.
	* config/rs6000/vector.md (div<mode>3): Ditto.

From-SVN: r241935
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce1f8e3d3174..8e6646b2715f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-11-07  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* config/rs6000/rs6000.md (div<mode>3): Expand using rs6000_emit_swdiv
+	if appropriate.
+	* config/rs6000/vector.md (div<mode>3): Ditto.
+
 2016-11-06  David Edelsohn  <dje.gcc@gmail.com>
 
 	* configure.ac (.hidden): Change to conftest_s string. Provide string
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 43270f82fb42..d40954989810 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4460,7 +4460,15 @@
 	(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
 		  (match_operand:SFDF 2 "gpc_reg_operand" "")))]
   "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
-  "")
+{
+  if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
+      && can_create_pseudo_p () && flag_finite_math_only
+      && !flag_trapping_math && flag_reciprocal_math)
+    {
+      rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
+      DONE;
+    }
+})
 
 (define_insn "*div<mode>3_fpr"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 7240345bce0e..05f3bdbee56a 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -248,7 +248,15 @@
 	(div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
 		   (match_operand:VEC_F 2 "vfloat_operand" "")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
-  "")
+{
+  if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
+      && can_create_pseudo_p () && flag_finite_math_only
+      && !flag_trapping_math && flag_reciprocal_math)
+    {
+      rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
+      DONE;
+    }
+})
 
 (define_expand "neg<mode>2"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")