From: Patrick O'Neill <patrick@rivosinc.com>
Date: Mon, 30 Oct 2023 22:51:46 +0000 (-0700)
Subject: RISC-V: Let non-atomic targets use optimized amo loads/stores
X-Git-Tag: basepoints/gcc-15~5097
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b93fddba394cf19d8a9fd1739314b6c57425be01;p=thirdparty%2Fgcc.git

RISC-V: Let non-atomic targets use optimized amo loads/stores

Non-atomic targets are currently prevented from using the optimized fencing for
seq_cst load/seq_cst store. This patch removes that constraint.

gcc/ChangeLog:

	* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Remove
	TARGET_ATOMIC constraint
	(atomic_store_rvwmo<mode>): Ditto.
	* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Ditto.
	(atomic_store_ztso<mode>): Ditto.
	* config/riscv/sync.md (atomic_load<mode>): Ditto.
	(atomic_store<mode>): Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---

diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index cb641ea9ec33..c35eae153342 100644
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -52,7 +52,7 @@
 	    [(match_operand:GPR 1 "memory_operand" "A")
 	     (match_operand:SI 2 "const_int_operand")]  ;; model
 	 UNSPEC_ATOMIC_LOAD))]
-  "TARGET_ATOMIC && !TARGET_ZTSO"
+  "!TARGET_ZTSO"
   {
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
@@ -78,7 +78,7 @@
 	    [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
 	     (match_operand:SI 2 "const_int_operand")]  ;; model
 	 UNSPEC_ATOMIC_STORE))]
-  "TARGET_ATOMIC && !TARGET_ZTSO"
+  "!TARGET_ZTSO"
   {
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 7bb15b7ab8cd..6fdfa912a2ca 100644
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -46,7 +46,7 @@
 	    [(match_operand:GPR 1 "memory_operand" "A")
 	     (match_operand:SI 2 "const_int_operand")]  ;; model
 	 UNSPEC_ATOMIC_LOAD))]
-  "TARGET_ATOMIC && TARGET_ZTSO"
+  "TARGET_ZTSO"
   {
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
@@ -66,7 +66,7 @@
 	    [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
 	     (match_operand:SI 2 "const_int_operand")]  ;; model
 	 UNSPEC_ATOMIC_STORE))]
-  "TARGET_ATOMIC && TARGET_ZTSO"
+  "TARGET_ZTSO"
   {
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 6ff3493b5ced..ec9d4b4f59ef 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -60,7 +60,7 @@
   [(match_operand:GPR 0 "register_operand")
    (match_operand:GPR 1 "memory_operand")
    (match_operand:SI 2 "const_int_operand")] ;; model
-  "TARGET_ATOMIC"
+  ""
   {
     if (TARGET_ZTSO)
       emit_insn (gen_atomic_load_ztso<mode> (operands[0], operands[1],
@@ -75,7 +75,7 @@
   [(match_operand:GPR 0 "memory_operand")
    (match_operand:GPR 1 "reg_or_0_operand")
    (match_operand:SI 2 "const_int_operand")] ;; model
-  "TARGET_ATOMIC"
+  ""
   {
     if (TARGET_ZTSO)
       emit_insn (gen_atomic_store_ztso<mode> (operands[0], operands[1],