From: Darshan Prajapati <darshan.prajapati@einfochips.com>
Date: Mon, 25 Aug 2025 13:24:22 +0000 (+0530)
Subject: dt-bindings: riscv: Add SiFive P550 CPU compatible
X-Git-Tag: v6.18-rc1~148^2~5
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b9607ff0f86ad310f4a5e6ac985b1e89d78fd3ec;p=thirdparty%2Fkernel%2Flinux.git

dt-bindings: riscv: Add SiFive P550 CPU compatible

Update Documentation for supporting SiFive P550 based CPU

Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250825132427.1618089-2-pinkesh.vaghela@einfochips.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 1a0cf0702a45d..153d0dac57fb3 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -52,6 +52,7 @@ properties:
               - sifive,e5
               - sifive,e7
               - sifive,e71
+              - sifive,p550
               - sifive,rocket0
               - sifive,s7
               - sifive,u5