From: Daniel Cederman <cederman@gaisler.com>
Date: Thu, 4 Jan 2024 13:56:06 +0000 (+0100)
Subject: sparc: Add errata workaround to membar patterns
X-Git-Tag: releases/gcc-13.3.0~552
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=b98ca776852fb9c7ab68a91099c40efaafaf9bf9;p=thirdparty%2Fgcc.git

sparc: Add errata workaround to membar patterns

LEON now uses the standard V8 membar patterns that contains an ldstub
instruction. This instruction needs to be aligned properly when the
GR712RC errata workaround is enabled.

gcc/ChangeLog:

	* config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
	* config/sparc/sync.md (membar_storeload): Turn into named insn
	and add GR712RC errata workaround.
	(membar_v8): Add GR712RC errata workaround.
---

diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 8c0c9dce9714..38aedd20054d 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -1063,6 +1063,7 @@ atomic_insn_for_leon3_p (rtx_insn *insn)
 {
   switch (INSN_CODE (insn))
     {
+    case CODE_FOR_membar_storeload:
     case CODE_FOR_swapsi:
     case CODE_FOR_ldstub:
     case CODE_FOR_atomic_compare_and_swap_leon3_1:
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index dfa128f2488b..e065b7287bdb 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -65,12 +65,19 @@
   [(set_attr "type" "multi")])
 
 ;; For V8, LDSTUB has the effect of membar #StoreLoad.
-(define_insn "*membar_storeload"
+(define_insn "membar_storeload"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
   "TARGET_V8"
-  "ldstub\t[%%sp-1], %%g0"
-  [(set_attr "type" "multi")])
+{
+  if (sparc_fix_gr712rc)
+    return ".align\t16\n\tldstub\t[%%sp-1], %%g0";
+  else
+    return "ldstub\t[%%sp-1], %%g0";
+}
+  [(set_attr "type" "multi")
+   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+		      (const_int 4) (const_int 1)))])
 
 ;; Put the two together, in combination with the fact that V8 implements PSO
 ;; as its weakest memory model, means a full barrier.  Match all remaining
@@ -80,9 +87,15 @@
 	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
 		    UNSPEC_MEMBAR))]
   "TARGET_V8"
-  "stbar\n\tldstub\t[%%sp-1], %%g0"
+{
+  if (sparc_fix_gr712rc)
+    return "stbar\n.align\t16\n\tldstub\t[%%sp-1], %%g0";
+  else
+    return "stbar\n\tldstub\t[%%sp-1], %%g0";
+}
   [(set_attr "type" "multi")
-   (set_attr "length" "2")])
+   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+		      (const_int 5) (const_int 2)))])
 
 ;; For V9, we have the full membar instruction.
 (define_insn "*membar"