From: Sneh Mankad Date: Fri, 29 May 2026 12:55:44 +0000 (+0530) Subject: pinctrl: qcom: Modify MSM_PULL_MASK to accurately represent PULL bits X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ba80761235bb526e7700468baaa9bddffebc3320;p=thirdparty%2Flinux.git pinctrl: qcom: Modify MSM_PULL_MASK to accurately represent PULL bits MSM_PULL_MASK currently spans bits [2:0], but the GPIO_PULL field in the GPIO_CFG register only occupies bits [1:0]. Bit 2 belongs to FUNC_SEL. MSM_PULL_MASK is used to isolate the GPIO_PULL bits before writing the pull configuration (PULL_DOWN: 0x1, PULL_UP: 0x3) to the GPIO_CFG register. Narrow it to bits [1:0] to prevent unintended modification of the FUNC_SEL field. This causes no functional change since the driver currently does not modify the FUNC_SEL bit, but align the mask with hardware configuration nonetheless. Signed-off-by: Sneh Mankad Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Linus Walleij --- diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 7d7fff538755a..b655de5b4c5f0 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -33,7 +33,7 @@ * dynamically, rather then relying on e.g. Devicetree and phandles. */ -#define MSM_PULL_MASK GENMASK(2, 0) +#define MSM_PULL_MASK GENMASK(1, 0) #define MSM_PULL_DOWN 1 #define MSM_PULL_UP 3 #define TLMM_REG_SIZE 0x1000