From: Xi Ruoyao Date: Sun, 19 Jan 2025 13:26:59 +0000 (+0800) Subject: LoongArch: Correct the mode for mask{eq,ne}z X-Git-Tag: basepoints/gcc-16~2145 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bad9a7303a4b4ec8192e2ab5da49ab1a9cc86347;p=thirdparty%2Fgcc.git LoongArch: Correct the mode for mask{eq,ne}z For mask{eq,ne}z, rk is always compared with 0 in the full width, thus the mode for rk should be X. I found the issue reviewing a patch fixing a similar issue for RISC-V XTheadCondMov [1], but interestingly I cannot find a test case really blowing up on LoongArch. But as the issue is obvious enough let's fix it anyway so it won't blow up in the future. [1]: https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674004.html gcc/ChangeLog: * config/loongarch/loongarch.md (*sel_using_): Rename to ... (*sel_using_): ... here. (GPR2): Remove as nothing uses it now. --- diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 701f31fbb17..36d140a9e94 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -374,10 +374,6 @@ ;; from the same template. (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) -;; A copy of GPR that can be used when a pattern has two independent -;; modes. -(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) - ;; This mode iterator allows 16-bit and 32-bit GPR patterns and 32-bit 64-bit ;; FPR patterns to be generated from the same template. (define_mode_iterator JOIN_MODE [HI @@ -2507,11 +2503,11 @@ ;; Conditional move instructions. -(define_insn "*sel_using_" +(define_insn "*sel_using_" [(set (match_operand:GPR 0 "register_operand" "=r,r") (if_then_else:GPR - (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "r,r") - (const_int 0)) + (equality_op:X (match_operand:X 1 "register_operand" "r,r") + (const_int 0)) (match_operand:GPR 2 "reg_or_0_operand" "r,J") (match_operand:GPR 3 "reg_or_0_operand" "J,r")))] "register_operand (operands[2], mode)