From: Stefan Hajnoczi <stefanha@redhat.com>
Date: Mon, 21 Jul 2025 16:21:49 +0000 (-0400)
Subject: Merge tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu into staging
X-Git-Tag: v10.1.0-rc0~5
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bb153e7960b24fb31b36b4230e4d1d008ae2f129;p=thirdparty%2Fqemu.git

Merge tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu into staging

target-arm queue:
 * hvf: arm: Remove $pc from trace_hvf_data_abort()
 * target/arm: Correct encoding of Debug Communications Channel registers
 * hw/misc/ivshmem-pci: Improve error handling
 * target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode
 * host-utils: Drop workaround for buggy Apple Clang __builtin_subcll()
 * hw/misc/max78000_aes: Comment Internal Key Storage
 * docs: Fix Aspeed title
 * Implement a handful of missing FEAT_SVE_B16_B16 insns
 * Fix bugs in FMAXQV, FMINQV, etc
 * Fix assert in LD1Q decode
 * hvf: arm: Add permission check in GIC sysreg handlers
 * hvf: arm: Emulate ICC_RPR_EL1 accesses properly
 * accel/hvf: Display executable bit as 'X'

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# gpg: Signature made Mon 21 Jul 2025 09:02:16 EDT
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# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu:
  accel/hvf: Display executable bit as 'X'
  hvf: arm: Emulate ICC_RPR_EL1 accesses properly
  hvf: arm: Add permission check in GIC sysreg handlers
  target/arm: Make LD1Q decode and trans fn agree about a->u
  target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV
  target/arm: Don't nest H() macro calls in SVE DO_REDUCE
  target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
  target/arm: Add BFMLA, BFMLS (indexed)
  target/arm: Add BFMLA, BFMLS (vectors)
  target/arm: Add BFMUL (indexed)
  target/arm: Add BFMIN, BFMAX (predicated)
  target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)
  target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)
  docs: Fix Aspeed title
  hw/misc/max78000_aes: Comment Internal Key Storage
  host-utils: Drop workaround for buggy Apple Clang __builtin_subcll()
  target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode
  hw/misc/ivshmem-pci: Improve error handling
  target/arm: Correct encoding of Debug Communications Channel registers
  hvf: arm: Remove $pc from trace_hvf_data_abort()

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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