From: Bard Liao <bardliao@realtek.com>
Date: Tue, 28 Apr 2015 03:27:39 +0000 (+0800)
Subject: ASoC: rt5677: fixed wrong DMIC ref clock
X-Git-Tag: v4.0.3~27
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bbc8c97c8e7fb76e07478e19e96a7fa6e7421bec;p=thirdparty%2Fkernel%2Fstable.git

ASoC: rt5677: fixed wrong DMIC ref clock

commit 60a8d62b8497c23eb3d48149af7e55dac2dd83a2 upstream.

DMIC clock source is not from codec system clock directly. it is
generated from the division of system clock. And it should be 256 *
sample rate of AIF1.

Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---

diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index b7f3644ab6c12..97b33e96439a3 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -904,7 +904,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 	struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
-	int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
+	int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
 
 	if (idx < 0)
 		dev_err(codec->dev, "Failed to set DMIC clock\n");