From: Oliver Upton <oliver.upton@linux.dev>
Date: Sun, 14 Jul 2024 00:28:30 +0000 (+0000)
Subject: Merge branch kvm-arm64/nv-tcr2 into kvmarm/next
X-Git-Tag: v6.11-rc1~89^2~17^2~1
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=bc2e3253ca965fc6a2df1ba242cf10a4ef9462f1;p=thirdparty%2Fkernel%2Flinux.git

Merge branch kvm-arm64/nv-tcr2 into kvmarm/next

* kvm-arm64/nv-tcr2:
  : Fixes to the handling of TCR_EL1, courtesy of Marc Zyngier
  :
  : Series addresses a couple gaps that are present in KVM (from cover
  : letter):
  :
  :   - VM configuration: HCRX_EL2.TCR2En is forced to 1, and we blindly
  :     save/restore stuff.
  :
  :   - trap bit description and routing: none, obviously, since we make a
  :     point in not trapping.
  KVM: arm64: Honor trap routing for TCR2_EL1
  KVM: arm64: Make PIR{,E0}_EL1 save/restore conditional on FEAT_TCRX
  KVM: arm64: Make TCR2_EL1 save/restore dependent on the VM features
  KVM: arm64: Get rid of HCRX_GUEST_FLAGS
  KVM: arm64: Correctly honor the presence of FEAT_TCRX

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---

bc2e3253ca965fc6a2df1ba242cf10a4ef9462f1
diff --cc arch/arm64/kvm/emulate-nested.c
index 96b837fe51562,2fa2d5fc37d60..05166eccea0a6
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@@ -79,10 -79,8 +79,12 @@@ enum cgt_group_id 
  	CGT_MDCR_E2TB,
  	CGT_MDCR_TDCC,
  
 +	CGT_CPACR_E0POE,
 +	CGT_CPTR_TAM,
 +	CGT_CPTR_TCPAC,
 +
+ 	CGT_HCRX_TCR2En,
+ 
  	/*
  	 * Anything after this point is a combination of coarse trap
  	 * controls, which must all be evaluated to decide what to do.
@@@ -351,24 -348,12 +354,30 @@@ static const struct trap_bits coarse_tr
  		.mask		= MDCR_EL2_TDCC,
  		.behaviour	= BEHAVE_FORWARD_ANY,
  	},
 +	[CGT_CPACR_E0POE] = {
 +		.index		= CPTR_EL2,
 +		.value		= CPACR_ELx_E0POE,
 +		.mask		= CPACR_ELx_E0POE,
 +		.behaviour	= BEHAVE_FORWARD_ANY,
 +	},
 +	[CGT_CPTR_TAM] = {
 +		.index		= CPTR_EL2,
 +		.value		= CPTR_EL2_TAM,
 +		.mask		= CPTR_EL2_TAM,
 +		.behaviour	= BEHAVE_FORWARD_ANY,
 +	},
 +	[CGT_CPTR_TCPAC] = {
 +		.index		= CPTR_EL2,
 +		.value		= CPTR_EL2_TCPAC,
 +		.mask		= CPTR_EL2_TCPAC,
 +		.behaviour	= BEHAVE_FORWARD_ANY,
 +	},
+ 	[CGT_HCRX_TCR2En] = {
+ 		.index		= HCRX_EL2,
+ 		.value 		= 0,
+ 		.mask		= HCRX_EL2_TCR2En,
+ 		.behaviour	= BEHAVE_FORWARD_ANY,
+ 	},
  };
  
  #define MCB(id, ...)						\
diff --cc arch/arm64/kvm/sys_regs.c
index 832c6733db307,8e22232c4b0f4..c90324060436b
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -4531,17 -4060,15 +4537,23 @@@ static void vcpu_set_hcr(struct kvm_vcp
  	 */
  	if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
  		vcpu->arch.hcr_el2 |= HCR_TTLBOS;
 +}
 +
 +void kvm_calculate_traps(struct kvm_vcpu *vcpu)
 +{
 +	struct kvm *kvm = vcpu->kvm;
 +
 +	mutex_lock(&kvm->arch.config_lock);
 +	vcpu_set_hcr(vcpu);
  
  	if (cpus_have_final_cap(ARM64_HAS_HCX)) {
- 		vcpu->arch.hcrx_el2 = HCRX_GUEST_FLAGS;
+ 		/*
+ 		 * In general, all HCRX_EL2 bits are gated by a feature.
+ 		 * The only reason we can set SMPME without checking any
+ 		 * feature is that its effects are not directly observable
+ 		 * from the guest.
+ 		 */
+ 		vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME;
  
  		if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP))
  			vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);