From: Haochen Jiang Date: Wed, 14 May 2025 06:57:41 +0000 (+0800) Subject: i386: Remove avx10.1-256/512 and evex512 options X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c052a6f4a1c803cb92147ff98fb91cf3511e0856;p=thirdparty%2Fgcc.git i386: Remove avx10.1-256/512 and evex512 options As we mentioned in GCC 15, we will remove avx10.1-256/512 and evex512 in GCC 16. Also, the combination of AVX10 and AVX512 option behavior will also be simplified in GCC 16 since AVX10.1 now implied AVX512, making the behavior matching everyone else. gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Remove feature set for AVX10_1_256. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_EVEX512_SET): Removed. (OPTION_MASK_ISA2_AVX10_1_256_SET): Removed. (OPTION_MASK_ISA_AVX10_1_SET): Imply all AVX512 features. (OPTION_MASK_ISA2_AVX10_1_SET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Remove AVX10_1_UNSET. (OPTION_MASK_ISA2_EVEX512_UNSET): Removed. (OPTION_MASK_ISA2_AVX10_1_UNSET): Remove AVX10_1_256. (OPTION_MASK_ISA2_AVX512F_UNSET): Unset AVX10_1. (ix86_handle_option): Remove special handling for AVX512/AVX10.1 options, evex512 and avx10_1_256. Modify ISA set for AVX10 options. * common/config/i386/i386-cpuinfo.h (enum feature_priority): Remove P_AVX10_1_256. (enum processor_features): Remove FEATURE_AVX10_1_256. * common/config/i386/i386-isas.h: Remove avx10.1-256/512. * config/i386/avx512bf16intrin.h: Rollback target push before evex512 is introduced. * config/i386/avx512bf16vlintrin.h: Ditto. * config/i386/avx512bitalgintrin.h: Ditto. * config/i386/avx512bitalgvlintrin.h: Ditto. * config/i386/avx512bwintrin.h: Ditto. * config/i386/avx512cdintrin.h: Ditto. * config/i386/avx512dqintrin.h: Ditto. * config/i386/avx512fintrin.h: Ditto. * config/i386/avx512fp16intrin.h: Ditto. * config/i386/avx512fp16vlintrin.h: Ditto. * config/i386/avx512ifmaintrin.h: Ditto. * config/i386/avx512ifmavlintrin.h: Ditto. * config/i386/avx512vbmi2intrin.h: Ditto. * config/i386/avx512vbmi2vlintrin.h: Ditto. * config/i386/avx512vbmiintrin.h: Ditto. * config/i386/avx512vbmivlintrin.h: Ditto. * config/i386/avx512vlbwintrin.h: Ditto. * config/i386/avx512vldqintrin.h: Ditto. * config/i386/avx512vlintrin.h: Ditto. * config/i386/avx512vnniintrin.h: Ditto. * config/i386/avx512vnnivlintrin.h: Ditto. * config/i386/avx512vp2intersectintrin.h: Ditto. * config/i386/avx512vp2intersectvlintrin.h: Ditto. * config/i386/avx512vpopcntdqintrin.h: Ditto. * config/i386/avx512vpopcntdqvlintrin.h: Ditto. * config/i386/gfniintrin.h: Ditto. * config/i386/vaesintrin.h: Ditto. * config/i386/vpclmulqdqintrin.h: Ditto. * config/i386/driver-i386.cc (check_avx512_features): Removed. (host_detect_local_cpu): Remove -march=native special handling. * config/i386/i386-builtins.cc (ix86_vectorize_builtin_gather): Remove TARGET_EVEX512. * config/i386/i386-c.cc (ix86_target_macros_internal): Remove EVEX512 and AVX10_1_256. * config/i386/i386-expand.cc (ix86_valid_mask_cmp_mode): Remove TARGET_EVEX512. (ix86_expand_int_sse_cmp): Ditto. (ix86_vector_duplicate_simode_const): Ditto. (ix86_expand_vector_init_duplicate): Ditto. (ix86_expand_vector_init_one_nonzero): Ditto. (ix86_emit_swsqrtsf): Ditto. (ix86_vectorize_vec_perm_const): Ditto. (ix86_expand_vecop_qihi2): Ditto. (ix86_expand_sse2_mulvxdi3): Ditto. (ix86_gen_bcst_mem): Ditto. * config/i386/i386-isa.def (EVEX512): Removed. (AVX10_1_256): Ditto. * config/i386/i386-options.cc (isa2_opts): Remove evex512 and avx10.1-256. (ix86_function_specific_save): Remove no_avx512_explicit and no_avx10_1_explicit. (ix86_function_specific_restore): Ditto. (ix86_valid_target_attribute_inner_p): Remove evex512 and avx10.1-256/512. (ix86_valid_target_attribute_tree): Remove special handling to rerun ix86_option_override_internal for AVX10.1-256. (ix86_option_override_internal): Remove warning handling. (ix86_simd_clone_adjust): Remove evex512. * config/i386/i386.cc (type_natural_mode): Remove TARGET_EVEX512. (ix86_return_in_memory): Ditto. (standard_sse_constant_p): Ditto. (standard_sse_constant_opcode): Ditto. (ix86_get_ssemov): Ditto. (ix86_legitimate_constant_p): Ditto. (ix86_vectorize_builtin_scatter): Ditto. (ix86_hard_regno_mode_ok): Ditto. (ix86_set_reg_reg_cost): Ditto. (ix86_rtx_costs): Ditto. (ix86_vector_mode_supported_p): Ditto. (ix86_preferred_simd_mode): Ditto. (ix86_autovectorize_vector_modes): Ditto. (ix86_get_mask_mode): Ditto. (ix86_simd_clone_compute_vecsize_and_simdlen): Ditto. (ix86_simd_clone_usable): Ditto. * config/i386/i386.h (BIGGEST_ALIGNMENT): Ditto. (MOVE_MAX): Ditto. (STORE_MAX_PIECES): Ditto. (PTA_SKYLAKE_AVX512): Remove PTA_EVEX512. (PTA_CANNONLAKE): Ditto. (PTA_ZNVER4): Ditto. (PTA_GRANITERAPIDS): Use PTA_AVX10_1. (PTA_DIAMONDRAPIDS): Use PTA_GRANITERAPIDS. * config/i386/i386.md: Remove TARGET_EVEX512, avx512f_512 and avx512bw_512. * config/i386/i386.opt: Remove ix86_no_avx512_explicit, ix86_no_avx10_1_explicit, mevex512, mavx10.1-256/512 and warning for mavx10.1. Modify option comment. * config/i386/i386.opt.urls: Remove evex512 and avx10.1-256/512. * config/i386/predicates.md: Remove TARGET_EVEX512. * config/i386/sse.md: Ditto. * doc/extend.texi: Remove avx10.1-256/512. Modify avx10.1 doc. * doc/invoke.texi: Remove avx10.1-256/512 and evex512. * doc/sourcebuild.texi: Remove avx10.1-256/512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: Remove warning. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/pr111068.c: Ditto. * gcc.target/i386/pr117946.c: Ditto. * gcc.target/i386/pr117240_avx512f.c: Remove -mevex512 and warning. * gcc.target/i386/avx10_1-11.c: Rename to ... * gcc.target/i386/avx10_1-5.c: ... this. Remove warning. * gcc.target/i386/avx10_1-12.c: Rename to ... * gcc.target/i386/avx10_1-6.c: ... this. Remove warning. * gcc.target/i386/avx10_1-26.c: Rename to ... * gcc.target/i386/avx10_1-7.c: ... this. Remove warning. The origin avx10_1-7.c is removed. * gcc.target/i386/avx10_1-10.c: Removed. * gcc.target/i386/avx10_1-13.c: Removed. * gcc.target/i386/avx10_1-14.c: Removed. * gcc.target/i386/avx10_1-15.c: Removed. * gcc.target/i386/avx10_1-16.c: Removed. * gcc.target/i386/avx10_1-17.c: Removed. * gcc.target/i386/avx10_1-18.c: Removed. * gcc.target/i386/avx10_1-19.c: Removed. * gcc.target/i386/avx10_1-20.c: Removed. * gcc.target/i386/avx10_1-21.c: Removed. * gcc.target/i386/avx10_1-22.c: Removed. * gcc.target/i386/avx10_1-23.c: Removed. * gcc.target/i386/avx10_1-8.c: Removed. * gcc.target/i386/avx10_1-9.c: Removed. * gcc.target/i386/noevex512-1.c: Removed. * gcc.target/i386/noevex512-2.c: Removed. * gcc.target/i386/noevex512-3.c: Removed. * gcc.target/i386/pr111889.c: Removed. * gcc.target/i386/pr111907.c: Removed. --- diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index e7e575c79d45..c93ea07239ad 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -1044,11 +1044,9 @@ get_available_features (struct __processor_model *cpu_model, /* Fall through. */ case 1: set_feature (FEATURE_AVX10_1); - set_feature (FEATURE_AVX10_1_256); break; default: set_feature (FEATURE_AVX10_1); - set_feature (FEATURE_AVX10_1_256); break; } } diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 296df3b32304..64908ce740a9 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -117,11 +117,17 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4 #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F -#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR -#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256 +#define OPTION_MASK_ISA_AVX10_1_SET \ + (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \ + | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \ + | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \ + | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \ + | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ + | OPTION_MASK_ISA_AVX512BITALG_SET) #define OPTION_MASK_ISA2_AVX10_1_SET \ - (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1) + (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \ + | OPTION_MASK_ISA2_AVX10_1) #define OPTION_MASK_ISA2_AVX10_2_SET \ (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2) #define OPTION_MASK_ISA2_AMX_AVX512_SET \ @@ -245,8 +251,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX2_UNSET \ (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ - | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ - | OPTION_MASK_ISA2_AVX10_1_UNSET) + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ @@ -320,11 +325,9 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F -#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR #define OPTION_MASK_ISA2_AVX10_1_UNSET \ - (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1 \ - | OPTION_MASK_ISA2_AVX10_2_UNSET) + (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET) #define OPTION_MASK_ISA2_AVX10_2_UNSET \ (OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AMX_AVX512_UNSET) #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512 @@ -375,7 +378,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX512F_UNSET \ (OPTION_MASK_ISA2_AVX512BW_UNSET \ - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ + | OPTION_MASK_ISA2_AVX10_1_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET \ @@ -632,7 +636,6 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -646,7 +649,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -865,7 +867,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -881,7 +882,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -895,7 +895,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -911,7 +910,6 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -926,7 +924,6 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -942,7 +939,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1010,7 +1006,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1026,7 +1021,6 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1040,7 +1034,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1054,7 +1047,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1068,7 +1060,6 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; - opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1335,20 +1326,6 @@ ix86_handle_option (struct gcc_options *opts, } return true; - case OPT_mevex512: - if (value) - { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_SET; - } - else - { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET; - opts->x_ix86_no_avx512_explicit = 1; - } - return true; - case OPT_musermsr: if (value) { @@ -1362,35 +1339,18 @@ ix86_handle_option (struct gcc_options *opts, } return true; - case OPT_mavx10_1_256: - if (value) - { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; - } - else - { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; - opts->x_ix86_no_avx10_1_explicit = 1; - } - return true; - case OPT_mavx10_1: if (value) { opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET; } else { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; - opts->x_ix86_no_avx10_1_explicit = 1; } return true; @@ -1399,8 +1359,8 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET; } else { @@ -1414,8 +1374,8 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET; } else { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 6b2ab0a76714..c73a87dbbe2d 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -148,8 +148,7 @@ enum feature_priority P_AVX512F, P_PROC_AVX512F, P_X86_64_V4, - P_AVX10_1_256, - P_AVX10_1, + P_AVX10_1 = 34, P_PROC_AVX10_1, P_PROC_DYNAMIC }; @@ -266,8 +265,7 @@ enum processor_features FEATURE_SM4, FEATURE_APX_F, FEATURE_USER_MSR, - FEATURE_AVX10_1_256, - FEATURE_AVX10_1, + FEATURE_AVX10_1 = 114, FEATURE_AVX10_2 = 116, FEATURE_AMX_AVX512, FEATURE_AMX_TF32, diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 55af985f1603..379bb34ef3f4 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -183,9 +183,7 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4") ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf") ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr") - ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256") ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1, P_AVX10_1, "-mavx10.1") - ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1, P_AVX10_1, "-mavx10.1-512") ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2, P_NONE, "-mavx10.2") ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE, "-mamx-avx512") diff --git a/gcc/config/i386/avx512bf16intrin.h b/gcc/config/i386/avx512bf16intrin.h index 674010996221..6c087e6c39b8 100644 --- a/gcc/config/i386/avx512bf16intrin.h +++ b/gcc/config/i386/avx512bf16intrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BF16INTRIN_H_INCLUDED #define _AVX512BF16INTRIN_H_INCLUDED -#if !defined (__AVX512BF16__) || defined (__EVEX512__) +#if !defined (__AVX512BF16__) #pragma GCC push_options -#pragma GCC target("avx512bf16,no-evex512") +#pragma GCC target("avx512bf16") #define __DISABLE_AVX512BF16__ #endif /* __AVX512BF16__ */ @@ -42,17 +42,6 @@ _mm_cvtsbh_ss (__bf16 __A) return __builtin_ia32_cvtbf2sf (__A); } -#ifdef __DISABLE_AVX512BF16__ -#undef __DISABLE_AVX512BF16__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512BF16__ */ - -#if !defined (__AVX512BF16__) || !defined (__EVEX512__) -#pragma GCC push_options -#pragma GCC target("avx512bf16,evex512") -#define __DISABLE_AVX512BF16_512__ -#endif /* __AVX512BF16_512__ */ - /* Internal data types for implementing the intrinsics. */ typedef __bf16 __v32bf __attribute__ ((__vector_size__ (64))); @@ -155,8 +144,8 @@ _mm512_mask_cvtpbh_ps (__m512 __S, __mmask16 __U, __m256bh __A) (__m512i)_mm512_cvtepi16_epi32 ((__m256i)__A), 16))); } -#ifdef __DISABLE_AVX512BF16_512__ -#undef __DISABLE_AVX512BF16_512__ +#ifdef __DISABLE_AVX512BF16__ +#undef __DISABLE_AVX512BF16__ #pragma GCC pop_options #endif /* __DISABLE_AVX512BF16_512__ */ diff --git a/gcc/config/i386/avx512bf16vlintrin.h b/gcc/config/i386/avx512bf16vlintrin.h index ffaceac8a0e9..fd6d18323dd4 100644 --- a/gcc/config/i386/avx512bf16vlintrin.h +++ b/gcc/config/i386/avx512bf16vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BF16VLINTRIN_H_INCLUDED #define _AVX512BF16VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512BF16__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512BF16__) #pragma GCC push_options -#pragma GCC target("avx512bf16,avx512vl,no-evex512") +#pragma GCC target("avx512bf16,avx512vl") #define __DISABLE_AVX512BF16VL__ #endif /* __AVX512BF16__ */ diff --git a/gcc/config/i386/avx512bitalgintrin.h b/gcc/config/i386/avx512bitalgintrin.h index 301f1256137b..d7156f925489 100644 --- a/gcc/config/i386/avx512bitalgintrin.h +++ b/gcc/config/i386/avx512bitalgintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BITALGINTRIN_H_INCLUDED #define _AVX512BITALGINTRIN_H_INCLUDED -#if !defined (__AVX512BITALG__) || !defined (__EVEX512__) +#if !defined (__AVX512BITALG__) #pragma GCC push_options -#pragma GCC target("avx512bitalg,evex512") +#pragma GCC target("avx512bitalg") #define __DISABLE_AVX512BITALG__ #endif /* __AVX512BITALG__ */ diff --git a/gcc/config/i386/avx512bitalgvlintrin.h b/gcc/config/i386/avx512bitalgvlintrin.h index e4883cffc835..cf9cff6db768 100644 --- a/gcc/config/i386/avx512bitalgvlintrin.h +++ b/gcc/config/i386/avx512bitalgvlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BITALGVLINTRIN_H_INCLUDED #define _AVX512BITALGVLINTRIN_H_INCLUDED -#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || defined (__EVEX512__) +#if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512bitalg,avx512vl,no-evex512") +#pragma GCC target("avx512bitalg,avx512vl") #define __DISABLE_AVX512BITALGVL__ #endif /* __AVX512BITALGVL__ */ diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h index 47c4c03e796a..5e9eeaace19f 100644 --- a/gcc/config/i386/avx512bwintrin.h +++ b/gcc/config/i386/avx512bwintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512BWINTRIN_H_INCLUDED #define _AVX512BWINTRIN_H_INCLUDED -#if !defined (__AVX512BW__) || defined (__EVEX512__) +#if !defined (__AVX512BW__) #pragma GCC push_options -#pragma GCC target("avx512bw,no-evex512") +#pragma GCC target("avx512bw") #define __DISABLE_AVX512BW__ #endif /* __AVX512BW__ */ @@ -346,17 +346,6 @@ _kandn_mask64 (__mmask64 __A, __mmask64 __B) return (__mmask64) __builtin_ia32_kandndi ((__mmask64) __A, (__mmask64) __B); } -#ifdef __DISABLE_AVX512BW__ -#undef __DISABLE_AVX512BW__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512BW__ */ - -#if !defined (__AVX512BW__) || !defined (__EVEX512__) -#pragma GCC push_options -#pragma GCC target("avx512bw,evex512") -#define __DISABLE_AVX512BW_512__ -#endif /* __AVX512BW_512__ */ - /* Internal data types for implementing the intrinsics. */ typedef short __v32hi __attribute__ ((__vector_size__ (64))); typedef short __v32hi_u __attribute__ ((__vector_size__ (64), \ @@ -3369,8 +3358,8 @@ _mm512_bsrli_epi128 (__m512i __A, const int __N) #endif -#ifdef __DISABLE_AVX512BW_512__ -#undef __DISABLE_AVX512BW_512__ +#ifdef __DISABLE_AVX512BW__ +#undef __DISABLE_AVX512BW__ #pragma GCC pop_options #endif /* __DISABLE_AVX512BW_512__ */ diff --git a/gcc/config/i386/avx512cdintrin.h b/gcc/config/i386/avx512cdintrin.h index 206cc49224e0..5a92d253800c 100644 --- a/gcc/config/i386/avx512cdintrin.h +++ b/gcc/config/i386/avx512cdintrin.h @@ -30,7 +30,7 @@ #ifndef __AVX512CD__ #pragma GCC push_options -#pragma GCC target("avx512cd,evex512") +#pragma GCC target("avx512cd") #define __DISABLE_AVX512CD__ #endif /* __AVX512CD__ */ diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index 1d10225831dd..a7766b554c5c 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512DQINTRIN_H_INCLUDED #define _AVX512DQINTRIN_H_INCLUDED -#if !defined (__AVX512DQ__) || defined (__EVEX512__) +#if !defined (__AVX512DQ__) #pragma GCC push_options -#pragma GCC target("avx512dq,no-evex512") +#pragma GCC target("avx512dq") #define __DISABLE_AVX512DQ__ #endif /* __AVX512DQ__ */ @@ -639,17 +639,6 @@ _mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm) #endif -#ifdef __DISABLE_AVX512DQ__ -#undef __DISABLE_AVX512DQ__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512DQ__ */ - -#if !defined (__AVX512DQ__) || !defined (__EVEX512__) -#pragma GCC push_options -#pragma GCC target("avx512dq,evex512") -#define __DISABLE_AVX512DQ_512__ -#endif /* __AVX512DQ_512__ */ - extern __inline __m512d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm512_broadcast_f64x2 (__m128d __A) @@ -2897,9 +2886,9 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm) #endif -#ifdef __DISABLE_AVX512DQ_512__ -#undef __DISABLE_AVX512DQ_512__ +#ifdef __DISABLE_AVX512DQ__ +#undef __DISABLE_AVX512DQ__ #pragma GCC pop_options -#endif /* __DISABLE_AVX512DQ_512__ */ +#endif /* __DISABLE_AVX512DQ__ */ #endif /* _AVX512DQINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index 9160787e2397..4469f730dbf8 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512FINTRIN_H_INCLUDED #define _AVX512FINTRIN_H_INCLUDED -#if !defined (__AVX512F__) || defined (__EVEX512__) +#if !defined (__AVX512F__) #pragma GCC push_options -#pragma GCC target("avx512f,no-evex512") +#pragma GCC target("avx512f") #define __DISABLE_AVX512F__ #endif /* __AVX512F__ */ @@ -54,11 +54,12 @@ typedef enum _MM_MANT_SIGN_nan /* DEST = NaN if sign(SRC) = 1 */ } _MM_MANTISSA_SIGN_ENUM; -/* These _mm{,256}_avx512* intrins are duplicated from their _mm{,256}_* forms - from AVX2 or before. We need to add them to prevent target option mismatch - when calling AVX512 intrins implemented with these intrins under no-evex512 - function attribute. All AVX512 intrins calling those AVX2 intrins or - before will change their calls to these AVX512 version. */ +/* These _mm{,256}_avx512* intrins are initially duplicated from their + _mm{,256}_* forms from AVX2 or before. At that time, e need to add them + to prevent target option mismatch when calling AVX512 intrins implemented + with these intrins under no-evex512 function attribute. Thess intrins will + still be here to avoid huge changes. All AVX512 intrins calling those AVX2 + intrins or before have changed their calls to these AVX512 version. */ extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_avx512_undefined_ps (void) { @@ -3802,17 +3803,6 @@ _mm_mask_cmp_ss_mask (__mmask8 __M, __m128 __X, __m128 __Y, const int __P) #endif -#ifdef __DISABLE_AVX512F__ -#undef __DISABLE_AVX512F__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512F__ */ - -#if !defined (__AVX512F__) || !defined (__EVEX512__) -#pragma GCC push_options -#pragma GCC target("avx512f,evex512") -#define __DISABLE_AVX512F_512__ -#endif /* __AVX512F_512__ */ - /* Internal data types for implementing the intrinsics. */ typedef double __v8df __attribute__ ((__vector_size__ (64))); typedef float __v16sf __attribute__ ((__vector_size__ (64))); @@ -16609,9 +16599,9 @@ _mm512_mask_reduce_max_pd (__mmask8 __U, __m512d __A) #undef __MM512_REDUCE_OP -#ifdef __DISABLE_AVX512F_512__ -#undef __DISABLE_AVX512F_512__ +#ifdef __DISABLE_AVX512F__ +#undef __DISABLE_AVX512F__ #pragma GCC pop_options -#endif /* __DISABLE_AVX512F_512__ */ +#endif /* __DISABLE_AVX512F__ */ #endif /* _AVX512FINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512fp16intrin.h b/gcc/config/i386/avx512fp16intrin.h index f158f87ed71b..471ec05b3407 100644 --- a/gcc/config/i386/avx512fp16intrin.h +++ b/gcc/config/i386/avx512fp16intrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512FP16INTRIN_H_INCLUDED #define _AVX512FP16INTRIN_H_INCLUDED -#if !defined (__AVX512FP16__) || defined (__EVEX512__) +#if !defined (__AVX512FP16__) #pragma GCC push_options -#pragma GCC target("avx512fp16,no-evex512") +#pragma GCC target("avx512fp16") #define __DISABLE_AVX512FP16__ #endif /* __AVX512FP16__ */ @@ -2852,17 +2852,6 @@ _mm_maskz_fmul_round_sch (__mmask8 __A, __m128h __B, __m128h __C, const int __E) #define _mm_maskz_cmul_round_sch(U, A, B, R) \ _mm_maskz_fcmul_round_sch ((U), (A), (B), (R)) -#ifdef __DISABLE_AVX512FP16__ -#undef __DISABLE_AVX512FP16__ -#pragma GCC pop_options -#endif /* __DISABLE_AVX512FP16__ */ - -#if !defined (__AVX512FP16__) || !defined (__EVEX512__) -#pragma GCC push_options -#pragma GCC target("avx512fp16,evex512") -#define __DISABLE_AVX512FP16_512__ -#endif /* __AVX512FP16_512__ */ - typedef _Float16 __v32hf __attribute__ ((__vector_size__ (64))); typedef _Float16 __m512h __attribute__ ((__vector_size__ (64), __may_alias__)); typedef _Float16 __m512h_u __attribute__ ((__vector_size__ (64), \ @@ -7238,9 +7227,9 @@ _mm512_set1_pch (_Float16 _Complex __A) #define _mm512_maskz_cmul_round_pch(U, A, B, R) \ _mm512_maskz_fcmul_round_pch ((U), (A), (B), (R)) -#ifdef __DISABLE_AVX512FP16_512__ -#undef __DISABLE_AVX512FP16_512__ +#ifdef __DISABLE_AVX512FP16__ +#undef __DISABLE_AVX512FP16__ #pragma GCC pop_options -#endif /* __DISABLE_AVX512FP16_512__ */ +#endif /* __DISABLE_AVX512FP16__ */ #endif /* _AVX512FP16INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/avx512fp16vlintrin.h b/gcc/config/i386/avx512fp16vlintrin.h index 59e6c881c501..cb98310a5cc9 100644 --- a/gcc/config/i386/avx512fp16vlintrin.h +++ b/gcc/config/i386/avx512fp16vlintrin.h @@ -28,9 +28,9 @@ #ifndef __AVX512FP16VLINTRIN_H_INCLUDED #define __AVX512FP16VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512FP16__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512FP16__) #pragma GCC push_options -#pragma GCC target("avx512fp16,avx512vl,no-evex512") +#pragma GCC target("avx512fp16,avx512vl") #define __DISABLE_AVX512FP16VL__ #endif /* __AVX512FP16VL__ */ diff --git a/gcc/config/i386/avx512ifmaintrin.h b/gcc/config/i386/avx512ifmaintrin.h index ed973505171f..56790c0ce446 100644 --- a/gcc/config/i386/avx512ifmaintrin.h +++ b/gcc/config/i386/avx512ifmaintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512IFMAINTRIN_H_INCLUDED #define _AVX512IFMAINTRIN_H_INCLUDED -#if !defined (__AVX512IFMA__) || !defined (__EVEX512__) +#if !defined (__AVX512IFMA__) #pragma GCC push_options -#pragma GCC target("avx512ifma,evex512") +#pragma GCC target("avx512ifma") #define __DISABLE_AVX512IFMA__ #endif /* __AVX512IFMA__ */ diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h index 681bda31097f..6b849c8d69b9 100644 --- a/gcc/config/i386/avx512ifmavlintrin.h +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512IFMAVLINTRIN_H_INCLUDED #define _AVX512IFMAVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512IFMA__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512IFMA__) #pragma GCC push_options -#pragma GCC target("avx512ifma,avx512vl,no-evex512") +#pragma GCC target("avx512ifma,avx512vl") #define __DISABLE_AVX512IFMAVL__ #endif /* __AVX512IFMAVL__ */ diff --git a/gcc/config/i386/avx512vbmi2intrin.h b/gcc/config/i386/avx512vbmi2intrin.h index f5515a8910d8..e8bfe1dd7983 100644 --- a/gcc/config/i386/avx512vbmi2intrin.h +++ b/gcc/config/i386/avx512vbmi2intrin.h @@ -28,9 +28,9 @@ #ifndef __AVX512VBMI2INTRIN_H_INCLUDED #define __AVX512VBMI2INTRIN_H_INCLUDED -#if !defined(__AVX512VBMI2__) || !defined (__EVEX512__) +#if !defined(__AVX512VBMI2__) #pragma GCC push_options -#pragma GCC target("avx512vbmi2,evex512") +#pragma GCC target("avx512vbmi2") #define __DISABLE_AVX512VBMI2__ #endif /* __AVX512VBMI2__ */ diff --git a/gcc/config/i386/avx512vbmi2vlintrin.h b/gcc/config/i386/avx512vbmi2vlintrin.h index e9857ba91129..5cdfebdc7e83 100644 --- a/gcc/config/i386/avx512vbmi2vlintrin.h +++ b/gcc/config/i386/avx512vbmi2vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VBMI2VLINTRIN_H_INCLUDED #define _AVX512VBMI2VLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__) #pragma GCC push_options -#pragma GCC target("avx512vbmi2,avx512vl,no-evex512") +#pragma GCC target("avx512vbmi2,avx512vl") #define __DISABLE_AVX512VBMI2VL__ #endif /* __AVX512VBMIVL__ */ diff --git a/gcc/config/i386/avx512vbmiintrin.h b/gcc/config/i386/avx512vbmiintrin.h index 901a2f7c9d02..5f5e34256813 100644 --- a/gcc/config/i386/avx512vbmiintrin.h +++ b/gcc/config/i386/avx512vbmiintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VBMIINTRIN_H_INCLUDED #define _AVX512VBMIINTRIN_H_INCLUDED -#if !defined (__AVX512VBMI__) || !defined (__EVEX512__) +#if !defined (__AVX512VBMI__) #pragma GCC push_options -#pragma GCC target("avx512vbmi,evex512") +#pragma GCC target("avx512vbmi") #define __DISABLE_AVX512VBMI__ #endif /* __AVX512VBMI__ */ diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h index 90cd5904d181..037ea93566a3 100644 --- a/gcc/config/i386/avx512vbmivlintrin.h +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VBMIVLINTRIN_H_INCLUDED #define _AVX512VBMIVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VBMI__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512VBMI__) #pragma GCC push_options -#pragma GCC target("avx512vbmi,avx512vl,no-evex512") +#pragma GCC target("avx512vbmi,avx512vl") #define __DISABLE_AVX512VBMIVL__ #endif /* __AVX512VBMIVL__ */ diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h index 9f0a5b489193..537e408a5bd5 100644 --- a/gcc/config/i386/avx512vlbwintrin.h +++ b/gcc/config/i386/avx512vlbwintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLBWINTRIN_H_INCLUDED #define _AVX512VLBWINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512BW__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512BW__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512bw,no-evex512") +#pragma GCC target("avx512vl,avx512bw") #define __DISABLE_AVX512VLBW__ #endif /* __AVX512VLBW__ */ diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index 3b23d4a207db..5783dbe4db36 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLDQINTRIN_H_INCLUDED #define _AVX512VLDQINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512DQ__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512DQ__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512dq,no-evex512") +#pragma GCC target("avx512vl,avx512dq") #define __DISABLE_AVX512VLDQ__ #endif /* __AVX512VLDQ__ */ diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h index 4451a1f6d26f..50930cd2ff4b 100644 --- a/gcc/config/i386/avx512vlintrin.h +++ b/gcc/config/i386/avx512vlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VLINTRIN_H_INCLUDED #define _AVX512VLINTRIN_H_INCLUDED -#if !defined (__AVX512VL__) || defined (__EVEX512__) +#if !defined (__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512vl,no-evex512") +#pragma GCC target("avx512vl") #define __DISABLE_AVX512VL__ #endif /* __AVX512VL__ */ @@ -13650,7 +13650,7 @@ _mm256_permutex_pd (__m256d __X, const int __M) #if !defined (__AVX512CD__) || !defined (__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512vl,avx512cd,no-evex512") +#pragma GCC target("avx512vl,avx512cd") #define __DISABLE_AVX512VLCD__ #endif diff --git a/gcc/config/i386/avx512vnniintrin.h b/gcc/config/i386/avx512vnniintrin.h index 5d0eaff30299..fe7b663d112b 100644 --- a/gcc/config/i386/avx512vnniintrin.h +++ b/gcc/config/i386/avx512vnniintrin.h @@ -28,9 +28,9 @@ #ifndef __AVX512VNNIINTRIN_H_INCLUDED #define __AVX512VNNIINTRIN_H_INCLUDED -#if !defined(__AVX512VNNI__) || !defined (__EVEX512__) +#if !defined(__AVX512VNNI__) #pragma GCC push_options -#pragma GCC target("avx512vnni,evex512") +#pragma GCC target("avx512vnni") #define __DISABLE_AVX512VNNI__ #endif /* __AVX512VNNI__ */ diff --git a/gcc/config/i386/avx512vnnivlintrin.h b/gcc/config/i386/avx512vnnivlintrin.h index 7774bbdfb2f7..01c3c91ee0d2 100644 --- a/gcc/config/i386/avx512vnnivlintrin.h +++ b/gcc/config/i386/avx512vnnivlintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VNNIVLINTRIN_H_INCLUDED #define _AVX512VNNIVLINTRIN_H_INCLUDED -#if !defined(__AVX512VL__) || !defined(__AVX512VNNI__) || defined (__EVEX512__) +#if !defined(__AVX512VL__) || !defined(__AVX512VNNI__) #pragma GCC push_options -#pragma GCC target("avx512vnni,avx512vl,no-evex512") +#pragma GCC target("avx512vnni,avx512vl") #define __DISABLE_AVX512VNNIVL__ #endif /* __AVX512VNNIVL__ */ diff --git a/gcc/config/i386/avx512vp2intersectintrin.h b/gcc/config/i386/avx512vp2intersectintrin.h index e170cf5c2cd5..50f7eada8b99 100644 --- a/gcc/config/i386/avx512vp2intersectintrin.h +++ b/gcc/config/i386/avx512vp2intersectintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VP2INTERSECTINTRIN_H_INCLUDED #define _AVX512VP2INTERSECTINTRIN_H_INCLUDED -#if !defined(__AVX512VP2INTERSECT__) || !defined (__EVEX512__) +#if !defined(__AVX512VP2INTERSECT__) #pragma GCC push_options -#pragma GCC target("avx512vp2intersect,evex512") +#pragma GCC target("avx512vp2intersect") #define __DISABLE_AVX512VP2INTERSECT__ #endif /* __AVX512VP2INTERSECT__ */ diff --git a/gcc/config/i386/avx512vp2intersectvlintrin.h b/gcc/config/i386/avx512vp2intersectvlintrin.h index afdd2daf2989..3e0a8abb6889 100644 --- a/gcc/config/i386/avx512vp2intersectvlintrin.h +++ b/gcc/config/i386/avx512vp2intersectvlintrin.h @@ -28,10 +28,9 @@ #ifndef _AVX512VP2INTERSECTVLINTRIN_H_INCLUDED #define _AVX512VP2INTERSECTVLINTRIN_H_INCLUDED -#if !defined(__AVX512VP2INTERSECT__) || !defined(__AVX512VL__) \ - || defined (__EVEX512__) +#if !defined(__AVX512VP2INTERSECT__) || !defined(__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512vp2intersect,avx512vl,no-evex512") +#pragma GCC target("avx512vp2intersect,avx512vl") #define __DISABLE_AVX512VP2INTERSECTVL__ #endif /* __AVX512VP2INTERSECTVL__ */ diff --git a/gcc/config/i386/avx512vpopcntdqintrin.h b/gcc/config/i386/avx512vpopcntdqintrin.h index 3357255baf65..e4b89ea4688d 100644 --- a/gcc/config/i386/avx512vpopcntdqintrin.h +++ b/gcc/config/i386/avx512vpopcntdqintrin.h @@ -28,9 +28,9 @@ #ifndef _AVX512VPOPCNTDQINTRIN_H_INCLUDED #define _AVX512VPOPCNTDQINTRIN_H_INCLUDED -#if !defined (__AVX512VPOPCNTDQ__) || !defined (__EVEX512__) +#if !defined (__AVX512VPOPCNTDQ__) #pragma GCC push_options -#pragma GCC target("avx512vpopcntdq,evex512") +#pragma GCC target("avx512vpopcntdq") #define __DISABLE_AVX512VPOPCNTDQ__ #endif /* __AVX512VPOPCNTDQ__ */ diff --git a/gcc/config/i386/avx512vpopcntdqvlintrin.h b/gcc/config/i386/avx512vpopcntdqvlintrin.h index 17d836fa5e82..8eb1d4243b6b 100644 --- a/gcc/config/i386/avx512vpopcntdqvlintrin.h +++ b/gcc/config/i386/avx512vpopcntdqvlintrin.h @@ -28,10 +28,9 @@ #ifndef _AVX512VPOPCNTDQVLINTRIN_H_INCLUDED #define _AVX512VPOPCNTDQVLINTRIN_H_INCLUDED -#if !defined(__AVX512VPOPCNTDQ__) || !defined(__AVX512VL__) \ - || defined (__EVEX512__) +#if !defined(__AVX512VPOPCNTDQ__) || !defined(__AVX512VL__) #pragma GCC push_options -#pragma GCC target("avx512vpopcntdq,avx512vl,no-evex512") +#pragma GCC target("avx512vpopcntdq,avx512vl") #define __DISABLE_AVX512VPOPCNTDQVL__ #endif /* __AVX512VPOPCNTDQVL__ */ diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 1ff05e52ab3d..63c7d79326d1 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -374,33 +374,6 @@ detect_caches_intel (bool xeon_mp, unsigned max_level, #define has_feature(f) \ has_cpu_feature (&cpu_model, cpu_features2, f) -/* We will emit a warning when using AVX10.1 and AVX512 options with one - enabled and the other disabled. Add this function to avoid push "-mno-" - options under this scenario for -march=native. */ - -bool check_avx512_features (__processor_model &cpu_model, - unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES], - const enum processor_features feature) -{ - if (has_feature (FEATURE_AVX10_1_256) - && ((feature == FEATURE_AVX512F) - || (feature == FEATURE_AVX512CD) - || (feature == FEATURE_AVX512DQ) - || (feature == FEATURE_AVX512BW) - || (feature == FEATURE_AVX512VL) - || (feature == FEATURE_AVX512IFMA) - || (feature == FEATURE_AVX512VBMI) - || (feature == FEATURE_AVX512VBMI2) - || (feature == FEATURE_AVX512VNNI) - || (feature == FEATURE_AVX512VPOPCNTDQ) - || (feature == FEATURE_AVX512BITALG) - || (feature == FEATURE_AVX512FP16) - || (feature == FEATURE_AVX512BF16))) - return false; - - return true; -} - /* This will be called by the spec parser in gcc.cc when it sees a %:local_cpu_detect(args) construct. Currently it will be called with either "arch [32|64]" or "tune [32|64]" as argument @@ -909,12 +882,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) options = concat (options, " ", isa_names_table[i].option, NULL); } - /* Never push -mno-avx10.1-{256,512} under -march=native to - avoid unnecessary warnings when building libraries. */ - else if (isa_names_table[i].feature != FEATURE_AVX10_1_256 - && isa_names_table[i].feature != FEATURE_AVX10_1 - && check_avx512_features (cpu_model, cpu_features2, - isa_names_table[i].feature)) + else options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); } diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h index c7e21e6de8bc..bc433c23a0ef 100644 --- a/gcc/config/i386/gfniintrin.h +++ b/gcc/config/i386/gfniintrin.h @@ -297,9 +297,9 @@ _mm256_maskz_gf2p8affine_epi64_epi8 (__mmask32 __A, __m256i __B, #pragma GCC pop_options #endif /* __GFNIAVX512VLBW__ */ -#if !defined(__GFNI__) || !defined(__EVEX512__) || !defined(__AVX512F__) +#if !defined(__GFNI__) || !defined(__AVX512F__) #pragma GCC push_options -#pragma GCC target("gfni,avx512f,evex512") +#pragma GCC target("gfni,avx512f") #define __DISABLE_GFNIAVX512F__ #endif /* __GFNIAVX512F__ */ @@ -341,9 +341,9 @@ _mm512_gf2p8affine_epi64_epi8 (__m512i __A, __m512i __B, const int __C) #pragma GCC pop_options #endif /* __GFNIAVX512F__ */ -#if !defined(__GFNI__) || !defined(__EVEX512__) || !defined(__AVX512BW__) +#if !defined(__GFNI__) || !defined(__AVX512BW__) #pragma GCC push_options -#pragma GCC target("gfni,avx512bw,evex512") +#pragma GCC target("gfni,avx512bw") #define __DISABLE_GFNIAVX512FBW__ #endif /* __GFNIAVX512FBW__ */ diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-builtins.cc index e88c3d65fbca..4835b949a2a8 100644 --- a/gcc/config/i386/i386-builtins.cc +++ b/gcc/config/i386/i386-builtins.cc @@ -1676,7 +1676,7 @@ ix86_vectorize_builtin_gather (const_tree mem_vectype, enum ix86_builtins code; const machine_mode mode = TYPE_MODE (TREE_TYPE (mem_vectype)); - if ((!TARGET_AVX512F || !TARGET_EVEX512) && GET_MODE_SIZE (mode) == 64) + if (!TARGET_AVX512F && GET_MODE_SIZE (mode) == 64) return NULL_TREE; if (! TARGET_AVX2 diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 0a320ca772a6..457aa05fca16 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -729,12 +729,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__SHA512__"); if (isa_flag2 & OPTION_MASK_ISA2_SM4) def_or_undef (parse_in, "__SM4__"); - if (isa_flag2 & OPTION_MASK_ISA2_EVEX512) - def_or_undef (parse_in, "__EVEX512__"); if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR) def_or_undef (parse_in, "__USER_MSR__"); - if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256) - def_or_undef (parse_in, "__AVX10_1_256__"); if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1) def_or_undef (parse_in, "__AVX10_1__"); if (isa_flag2 & OPTION_MASK_ISA2_APX_F) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index ae817d851f0f..7fd03c88630f 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -4188,7 +4188,7 @@ ix86_valid_mask_cmp_mode (machine_mode mode) if ((inner_mode == QImode || inner_mode == HImode) && !TARGET_AVX512BW) return false; - return (vector_size == 64 && TARGET_EVEX512) || TARGET_AVX512VL; + return vector_size == 64 || TARGET_AVX512VL; } /* Return true if integer mask comparison should be used. */ @@ -5026,7 +5026,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, && GET_MODE_SIZE (GET_MODE_INNER (mode)) >= 4 /* Don't do it if not using integer masks and we'd end up with the right values in the registers though. */ - && ((GET_MODE_SIZE (mode) == 64 && TARGET_EVEX512) + && (GET_MODE_SIZE (mode) == 64 || !vector_all_ones_operand (optrue, data_mode) || opfalse != CONST0_RTX (data_mode)))) { @@ -16189,7 +16189,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, { case VEC_BCAST_PXOR: if ((mode == V8SImode && !TARGET_AVX2) - || (mode == V16SImode && !(TARGET_AVX512F && TARGET_EVEX512))) + || (mode == V16SImode && !TARGET_AVX512F)) return false; emit_move_insn (target, CONST0_RTX (mode)); return true; @@ -16197,7 +16197,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, case VEC_BCAST_PCMPEQ: if ((mode == V4SImode && !TARGET_SSE2) || (mode == V8SImode && !TARGET_AVX2) - || (mode == V16SImode && !(TARGET_AVX512F && TARGET_EVEX512))) + || (mode == V16SImode && !TARGET_AVX512F)) return false; emit_move_insn (target, CONSTM1_RTX (mode)); return true; @@ -16217,7 +16217,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, tmp2 = gen_reg_rtx (V32QImode); emit_insn (gen_absv32qi2 (tmp2, tmp1)); } - else if (mode == V16SImode && TARGET_AVX512BW && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512BW) { tmp1 = gen_reg_rtx (V64QImode); emit_move_insn (tmp1, CONSTM1_RTX (V64QImode)); @@ -16243,7 +16243,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, tmp2 = gen_reg_rtx (V32QImode); emit_insn (gen_addv32qi3 (tmp2, tmp1, tmp1)); } - else if (mode == V16SImode && TARGET_AVX512BW && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512BW) { tmp1 = gen_reg_rtx (V64QImode); emit_move_insn (tmp1, CONSTM1_RTX (V64QImode)); @@ -16269,7 +16269,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, tmp2 = gen_reg_rtx (V16HImode); emit_insn (gen_lshrv16hi3 (tmp2, tmp1, GEN_INT (entry->arg))); } - else if (mode == V16SImode && TARGET_AVX512BW && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512BW) { tmp1 = gen_reg_rtx (V32HImode); emit_move_insn (tmp1, CONSTM1_RTX (V32HImode)); @@ -16295,7 +16295,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, emit_insn (gen_lshrv8si3 (target, tmp1, GEN_INT (entry->arg))); return true; } - else if (mode == V16SImode && TARGET_AVX512F && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512F) { tmp1 = gen_reg_rtx (V16SImode); emit_move_insn (tmp1, CONSTM1_RTX (V16SImode)); @@ -16321,7 +16321,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, tmp2 = gen_reg_rtx (V16HImode); emit_insn (gen_ashlv16hi3 (tmp2, tmp1, GEN_INT (entry->arg))); } - else if (mode == V16SImode && TARGET_AVX512BW && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512BW) { tmp1 = gen_reg_rtx (V32HImode); emit_move_insn (tmp1, CONSTM1_RTX (V32HImode)); @@ -16347,7 +16347,7 @@ ix86_vector_duplicate_simode_const (machine_mode mode, rtx target, emit_insn (gen_ashlv8si3 (target, tmp1, GEN_INT (entry->arg))); return true; } - else if (mode == V16SImode && TARGET_AVX512F && TARGET_EVEX512) + else if (mode == V16SImode && TARGET_AVX512F) { tmp1 = gen_reg_rtx (V16SImode); emit_move_insn (tmp1, CONSTM1_RTX (V16SImode)); @@ -16717,7 +16717,6 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, case E_V32HFmode: case E_V32BFmode: - gcc_assert (TARGET_EVEX512); if (TARGET_AVX512BW) return ix86_vector_duplicate_value (mode, target, val); else @@ -16770,9 +16769,6 @@ ix86_expand_vector_init_one_nonzero (bool mmx_ok, machine_mode mode, bool use_vector_set = false; rtx (*gen_vec_set_0) (rtx, rtx, rtx) = NULL; - if (GET_MODE_SIZE (mode) == 64 && !TARGET_EVEX512) - return false; - switch (mode) { case E_V2DImode: @@ -19434,7 +19430,7 @@ ix86_emit_swsqrtsf (rtx res, rtx a, machine_mode mode, bool recip) unsigned vector_size = GET_MODE_SIZE (mode); if (TARGET_FMA - || (TARGET_AVX512F && TARGET_EVEX512 && vector_size == 64) + || (TARGET_AVX512F && vector_size == 64) || (TARGET_AVX512VL && (vector_size == 32 || vector_size == 16))) emit_insn (gen_rtx_SET (e2, gen_rtx_FMA (mode, e0, x0, mthree))); @@ -24360,9 +24356,6 @@ ix86_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode, unsigned int i, nelt, which; bool two_args; - if (GET_MODE_SIZE (vmode) == 64 && !TARGET_EVEX512) - return false; - /* For HF and BF mode vector, convert it to HI using subreg. */ if (GET_MODE_INNER (vmode) == HFmode || GET_MODE_INNER (vmode) == BFmode) { @@ -24904,7 +24897,6 @@ ix86_expand_vecop_qihi2 (enum rtx_code code, rtx dest, rtx op1, rtx op2) ix86_expand_vecop_qihi. */ if (!TARGET_AVX512BW || (qimode == V16QImode && !TARGET_AVX512VL) - || (qimode == V32QImode && !TARGET_EVEX512) /* There are no V64HImode instructions. */ || qimode == V64QImode) return false; @@ -25373,7 +25365,7 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) machine_mode mode = GET_MODE (op0); rtx t1, t2, t3, t4, t5, t6; - if (TARGET_AVX512DQ && TARGET_EVEX512 && mode == V8DImode) + if (TARGET_AVX512DQ && mode == V8DImode) emit_insn (gen_avx512dq_mulv8di3 (op0, op1, op2)); else if (TARGET_AVX512DQ && TARGET_AVX512VL && mode == V4DImode) emit_insn (gen_avx512dq_mulv4di3 (op0, op1, op2)); @@ -26202,8 +26194,7 @@ ix86_gen_bcst_mem (machine_mode mode, rtx x) { if (!TARGET_AVX512F || !CONST_VECTOR_P (x) - || (!TARGET_AVX512VL - && (GET_MODE_SIZE (mode) != 64 || !TARGET_EVEX512)) + || (!TARGET_AVX512VL && GET_MODE_SIZE (mode) != 64) || !VALID_BCST_MODE_P (GET_MODE_INNER (mode)) /* Disallow HFmode broadcast. */ || GET_MODE_SIZE (GET_MODE_INNER (mode)) < 4) diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 19d78d7e44ea..6fa601d73c37 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -118,8 +118,6 @@ DEF_PTA(SHA512) DEF_PTA(SM4) DEF_PTA(APX_F) DEF_PTA(USER_MSR) -DEF_PTA(EVEX512) -DEF_PTA(AVX10_1_256) DEF_PTA(AVX10_1) DEF_PTA(AVX10_2) DEF_PTA(AMX_AVX512) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 45aa9b4b732f..124386735039 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -259,9 +259,7 @@ static struct ix86_target_opts isa2_opts[] = { "-msm3", OPTION_MASK_ISA2_SM3 }, { "-msha512", OPTION_MASK_ISA2_SHA512 }, { "-msm4", OPTION_MASK_ISA2_SM4 }, - { "-mevex512", OPTION_MASK_ISA2_EVEX512 }, { "-musermsr", OPTION_MASK_ISA2_USER_MSR }, - { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 }, { "-mavx10.1", OPTION_MASK_ISA2_AVX10_1 }, { "-mavx10.2", OPTION_MASK_ISA2_AVX10_2 }, { "-mamx-avx512", OPTION_MASK_ISA2_AMX_AVX512 }, @@ -713,8 +711,6 @@ ix86_function_specific_save (struct cl_target_option *ptr, ptr->x_ix86_apx_features = opts->x_ix86_apx_features; ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit; ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit; - ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit; - ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit; ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit; ptr->x_ix86_arch_string = opts->x_ix86_arch_string; ptr->x_ix86_tune_string = opts->x_ix86_tune_string; @@ -858,8 +854,6 @@ ix86_function_specific_restore (struct gcc_options *opts, opts->x_ix86_apx_features = ptr->x_ix86_apx_features; opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit; opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit; - opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit; - opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit; opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit; opts->x_ix86_arch_string = ptr->x_ix86_arch_string; opts->x_ix86_tune_string = ptr->x_ix86_tune_string; @@ -1131,11 +1125,8 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("sha512", OPT_msha512), IX86_ATTR_ISA ("sm4", OPT_msm4), IX86_ATTR_ISA ("apxf", OPT_mapxf), - IX86_ATTR_ISA ("evex512", OPT_mevex512), IX86_ATTR_ISA ("usermsr", OPT_musermsr), - IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256), IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1), - IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1), IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2), IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512), IX86_ATTR_ISA ("amx-tf32", OPT_mamx_tf32), @@ -1429,18 +1420,6 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, target_clone_attr)) return error_mark_node; - /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all - AVX512 related ISA flags and not setting EVEX512. When it is used - with avx512 related function attribute, we need to enable 512 bit to - align with the command line behavior. Manually set EVEX512 for this - scenario. */ - if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256) - && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F) - && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F) - && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; - /* If the changed options are different from the default, rerun ix86_option_override_internal, and then save the options away. The string options are attribute options, and will be undone @@ -1451,10 +1430,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, || option_strings[IX86_FUNCTION_SPECIFIC_ARCH] || option_strings[IX86_FUNCTION_SPECIFIC_TUNE] || enum_opts_set.x_ix86_fpmath - || enum_opts_set.x_prefer_vector_width_type - || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256) - && (opts->x_ix86_isa_flags2_explicit - & OPTION_MASK_ISA2_AVX10_1_256))) + || enum_opts_set.x_prefer_vector_width_type) { /* If we are using the default tune= or arch=, undo the string assigned, and use the default. */ @@ -2018,7 +1994,7 @@ ix86_option_override_internal (bool main_args_p, struct gcc_options *opts_set) { unsigned int i; - unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2; + unsigned HOST_WIDE_INT ix86_arch_mask; const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL); /* -mrecip options. */ @@ -2037,15 +2013,6 @@ ix86_option_override_internal (bool main_args_p, { "vec-sqrt", RECIP_MASK_VEC_SQRT }, }; - avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD - | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW - | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA - | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2 - | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ - | OPTION_MASK_ISA_AVX512BITALG; - avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16 - | OPTION_MASK_ISA2_AVX512BF16; - /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */ if (TARGET_64BIT_DEFAULT && !TARGET_64BIT_P (opts->x_ix86_isa_flags)) @@ -2667,107 +2634,6 @@ ix86_option_override_internal (bool main_args_p, &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM) & ~opts->x_ix86_isa_flags_explicit); - /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options except - for the following option combinations: - 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with no - explicit disable on other AVX512 features. - 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no - explicit disable on other AVX512 features. - 3. Both AVX10.1 and AVX512 are disabled. */ - if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2)) - { - if (opts->x_ix86_no_avx512_explicit - && (((~(avx512_isa_flags & opts->x_ix86_isa_flags) - & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit))) - || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512) - & opts->x_ix86_isa_flags2) - & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512) - & opts->x_ix86_isa_flags2_explicit))))) - warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable " - "AVX10 instructions when AVX10.1-512 is available in GCC 15, " - "behavior will change to it will disable that part of " - "AVX512 instructions since GCC 16"); - } - else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2)) - { - if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2) - && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit)) - { - if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags) - || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit)) - { - /* We should not emit 512 bit instructions under AVX10.1-256 - when EVEX512 is enabled w/o any AVX512 features enabled. - Disable EVEX512 bit for this. */ - warning (0, "Using %<-mevex512%> without any AVX512 features " - "enabled together with AVX10.1 only will not enable " - "any AVX512 or AVX10.1-512 features, using 256 as " - "max vector size"); - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512; - } - else - warning (0, "Vector size conflicts between AVX10.1 and AVX512, " - "using 512 as max vector size"); - } - else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) - && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F) - && !(OPTION_MASK_ISA2_EVEX512 - & opts->x_ix86_isa_flags2_explicit)) - warning (0, "Vector size conflicts between AVX10.1 and AVX512, using " - "512 as max vector size"); - else if (opts->x_ix86_no_avx512_explicit - && (((~(avx512_isa_flags & opts->x_ix86_isa_flags) - & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit))) - || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2) - & (avx512_isa_flags2 - & opts->x_ix86_isa_flags2_explicit))))) - warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions " - "when AVX10 is available in GCC 15, behavior will change " - "to it will disable that part of AVX512 instructions since " - "GCC 16"); - } - else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) - && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit)) - { - if (opts->x_ix86_no_avx10_1_explicit - && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1) - & opts->x_ix86_isa_flags2_explicit)) - { - warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> cannot disable " - "AVX512 instructions when %<-mavx512XXX%> in GCC 15, " - "behavior will change to it will disable all the " - "instructions in GCC 16"); - /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is - disabled. */ - if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit) - { - opts->x_ix86_isa_flags = (~avx512_isa_flags - & opts->x_ix86_isa_flags) - | (avx512_isa_flags & opts->x_ix86_isa_flags - & opts->x_ix86_isa_flags_explicit); - opts->x_ix86_isa_flags2 = (~avx512_isa_flags2 - & opts->x_ix86_isa_flags2) - | (avx512_isa_flags2 & opts->x_ix86_isa_flags2 - & opts->x_ix86_isa_flags2_explicit); - } - } - } - - /* Set EVEX512 if one of the following conditions meets: - 1. AVX512 is enabled while EVEX512 is not explicitly set/unset. - 2. AVX10.1-512 is enabled. */ - if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2) - || (TARGET_AVX512F_P (opts->x_ix86_isa_flags) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; - - /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */ - if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2)) - { - opts->x_ix86_isa_flags |= avx512_isa_flags; - opts->x_ix86_isa_flags2 |= avx512_isa_flags2; - } - /* Validate -mpreferred-stack-boundary= value or default it to PREFERRED_STACK_BOUNDARY_DEFAULT. */ ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT; @@ -3042,8 +2908,7 @@ ix86_option_override_internal (bool main_args_p, opts->x_ix86_move_max = opts->x_prefer_vector_width_type; if (opts_set->x_ix86_move_max == PVW_NONE) { - if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) - && TARGET_EVEX512_P (opts->x_ix86_isa_flags2)) + if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)) opts->x_ix86_move_max = PVW_AVX512; /* Align with vectorizer to avoid potential STLF issue. */ else if (TARGET_AVX_P (opts->x_ix86_isa_flags)) @@ -3069,8 +2934,7 @@ ix86_option_override_internal (bool main_args_p, opts->x_ix86_store_max = opts->x_prefer_vector_width_type; if (opts_set->x_ix86_store_max == PVW_NONE) { - if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) - && TARGET_EVEX512_P (opts->x_ix86_isa_flags2)) + if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)) opts->x_ix86_store_max = PVW_AVX512; /* Align with vectorizer to avoid potential STLF issue. */ else if (TARGET_AVX_P (opts->x_ix86_isa_flags)) @@ -3367,13 +3231,13 @@ ix86_simd_clone_adjust (struct cgraph_node *node) case 'e': if (TARGET_PREFER_AVX256) { - if (!TARGET_AVX512F || !TARGET_EVEX512) - str = "avx512f,evex512,prefer-vector-width=512"; + if (!TARGET_AVX512F) + str = "avx512f,prefer-vector-width=512"; else str = "prefer-vector-width=512"; } - else if (!TARGET_AVX512F || !TARGET_EVEX512) - str = "avx512f,evex512"; + else if (!TARGET_AVX512F) + str = "avx512f"; break; default: gcc_unreachable (); diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 7f6104100255..5cb66dadb43e 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -1997,8 +1997,7 @@ type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum, if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type) && GET_MODE_INNER (mode) == innermode) { - if (size == 64 && (!TARGET_AVX512F || !TARGET_EVEX512) - && !TARGET_IAMCU) + if (size == 64 && !TARGET_AVX512F && !TARGET_IAMCU) { static bool warnedavx512f; static bool warnedavx512f_ret; @@ -4421,7 +4420,7 @@ ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) /* AVX512F values are returned in ZMM0 if available. */ if (size == 64) - return !TARGET_AVX512F || !TARGET_EVEX512; + return !TARGET_AVX512F; } if (mode == XFmode) @@ -5375,7 +5374,7 @@ standard_sse_constant_p (rtx x, machine_mode pred_mode) switch (GET_MODE_SIZE (mode)) { case 64: - if (TARGET_AVX512F && TARGET_EVEX512) + if (TARGET_AVX512F) return 2; break; case 32: @@ -5428,10 +5427,8 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) { if (TARGET_AVX512VL) return "vpxord\t%x0, %x0, %x0"; - else if (TARGET_EVEX512) - return "vpxord\t%g0, %g0, %g0"; else - gcc_unreachable (); + return "vpxord\t%g0, %g0, %g0"; } return "vpxor\t%x0, %x0, %x0"; @@ -5447,19 +5444,15 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) { if (TARGET_AVX512VL) return "vxorpd\t%x0, %x0, %x0"; - else if (TARGET_EVEX512) - return "vxorpd\t%g0, %g0, %g0"; else - gcc_unreachable (); + return "vxorpd\t%g0, %g0, %g0"; } else { if (TARGET_AVX512VL) return "vpxorq\t%x0, %x0, %x0"; - else if (TARGET_EVEX512) - return "vpxorq\t%g0, %g0, %g0"; else - gcc_unreachable (); + return "vpxorq\t%g0, %g0, %g0"; } } return "vxorpd\t%x0, %x0, %x0"; @@ -5476,19 +5469,15 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) { if (TARGET_AVX512VL) return "vxorps\t%x0, %x0, %x0"; - else if (TARGET_EVEX512) - return "vxorps\t%g0, %g0, %g0"; else - gcc_unreachable (); + return "vxorps\t%g0, %g0, %g0"; } else { if (TARGET_AVX512VL) return "vpxord\t%x0, %x0, %x0"; - else if (TARGET_EVEX512) - return "vpxord\t%g0, %g0, %g0"; else - gcc_unreachable (); + return "vpxord\t%g0, %g0, %g0"; } } return "vxorps\t%x0, %x0, %x0"; @@ -5509,7 +5498,7 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) case MODE_XI: case MODE_V8DF: case MODE_V16SF: - gcc_assert (TARGET_AVX512F && TARGET_EVEX512); + gcc_assert (TARGET_AVX512F); return "vpternlogd\t{$0xFF, %g0, %g0, %g0|%g0, %g0, %g0, 0xFF}"; case MODE_OI: @@ -5525,10 +5514,8 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) { if (TARGET_AVX512VL) return "vpternlogd\t{$0xFF, %0, %0, %0|%0, %0, %0, 0xFF}"; - else if (TARGET_EVEX512) - return "vpternlogd\t{$0xFF, %g0, %g0, %g0|%g0, %g0, %g0, 0xFF}"; else - gcc_unreachable (); + return "vpternlogd\t{$0xFF, %g0, %g0, %g0|%g0, %g0, %g0, 0xFF}"; } return (TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" @@ -5542,7 +5529,7 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) { if (GET_MODE_SIZE (mode) == 64) { - gcc_assert (TARGET_AVX512F && TARGET_EVEX512); + gcc_assert (TARGET_AVX512F); return "vpcmpeqd\t%t0, %t0, %t0"; } else if (GET_MODE_SIZE (mode) == 32) @@ -5554,7 +5541,7 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) } else if (vector_all_ones_zero_extend_quarter_operand (x, mode)) { - gcc_assert (TARGET_AVX512F && TARGET_EVEX512); + gcc_assert (TARGET_AVX512F); return "vpcmpeqd\t%x0, %x0, %x0"; } @@ -5665,8 +5652,6 @@ ix86_get_ssemov (rtx *operands, unsigned size, || memory_operand (operands[1], mode)) gcc_unreachable (); size = 64; - /* We need TARGET_EVEX512 to move into zmm register. */ - gcc_assert (TARGET_EVEX512); switch (type) { case opcode_int: @@ -11419,7 +11404,7 @@ ix86_legitimate_constant_p (machine_mode mode, rtx x) case E_OImode: case E_XImode: if (!standard_sse_constant_p (x, mode) - && GET_MODE_SIZE (TARGET_AVX512F && TARGET_EVEX512 + && GET_MODE_SIZE (TARGET_AVX512F ? XImode : (TARGET_AVX ? OImode @@ -20316,14 +20301,10 @@ ix86_vectorize_builtin_scatter (const_tree vectype, { bool si; enum ix86_builtins code; - const machine_mode mode = TYPE_MODE (TREE_TYPE (vectype)); if (!TARGET_AVX512F) return NULL_TREE; - if (!TARGET_EVEX512 && GET_MODE_SIZE (mode) == 64) - return NULL_TREE; - if (known_eq (TYPE_VECTOR_SUBPARTS (vectype), 2u) ? !TARGET_USE_SCATTER_2PARTS : (known_eq (TYPE_VECTOR_SUBPARTS (vectype), 4u) @@ -21445,7 +21426,7 @@ ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode) - any of 512-bit wide vector mode - any scalar mode. */ if (TARGET_AVX512F - && ((VALID_AVX512F_REG_OR_XI_MODE (mode) && TARGET_EVEX512) + && ((VALID_AVX512F_REG_OR_XI_MODE (mode)) || VALID_AVX512F_SCALAR_MODE (mode))) return true; @@ -21687,7 +21668,7 @@ ix86_set_reg_reg_cost (machine_mode mode) case MODE_VECTOR_INT: case MODE_VECTOR_FLOAT: - if ((TARGET_AVX512F && TARGET_EVEX512 && VALID_AVX512F_REG_MODE (mode)) + if ((TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) || (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) || (TARGET_SSE && VALID_SSE_REG_MODE (mode)) @@ -22143,9 +22124,9 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, /* Handling different vternlog variants. */ if ((GET_MODE_SIZE (mode) == 64 - ? (TARGET_AVX512F && TARGET_EVEX512) + ? TARGET_AVX512F : (TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256))) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256))) && GET_MODE_SIZE (mode) >= 16 && outer_code_i == SET && ternlog_operand (x, mode)) @@ -22494,8 +22475,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, { /* (ior (not ...) ...) can be a single insn in AVX512. */ if (GET_CODE (XEXP (x, 0)) == NOT && TARGET_AVX512F - && ((TARGET_EVEX512 - && GET_MODE_SIZE (mode) == 64) + && (GET_MODE_SIZE (mode) == 64 || (TARGET_AVX512VL && (GET_MODE_SIZE (mode) == 32 || GET_MODE_SIZE (mode) == 16)))) @@ -22586,8 +22566,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, /* (and (not ...) (not ...)) can be a single insn in AVX512. */ if (GET_CODE (right) == NOT && TARGET_AVX512F - && ((TARGET_EVEX512 - && GET_MODE_SIZE (mode) == 64) + && (GET_MODE_SIZE (mode) == 64 || (TARGET_AVX512VL && (GET_MODE_SIZE (mode) == 32 || GET_MODE_SIZE (mode) == 16)))) @@ -22657,8 +22636,7 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, { /* (not (xor ...)) can be a single insn in AVX512. */ if (GET_CODE (XEXP (x, 0)) == XOR && TARGET_AVX512F - && ((TARGET_EVEX512 - && GET_MODE_SIZE (mode) == 64) + && (GET_MODE_SIZE (mode) == 64 || (TARGET_AVX512VL && (GET_MODE_SIZE (mode) == 32 || GET_MODE_SIZE (mode) == 16)))) @@ -24570,7 +24548,7 @@ ix86_vector_mode_supported_p (machine_mode mode) return true; if (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) return true; - if (TARGET_AVX512F && TARGET_EVEX512 && VALID_AVX512F_REG_MODE (mode)) + if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) return true; if ((TARGET_MMX || TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode)) @@ -25367,7 +25345,7 @@ ix86_preferred_simd_mode (scalar_mode mode) switch (mode) { case E_QImode: - if (TARGET_AVX512BW && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512BW && !TARGET_PREFER_AVX256) return V64QImode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V32QImode; @@ -25375,7 +25353,7 @@ ix86_preferred_simd_mode (scalar_mode mode) return V16QImode; case E_HImode: - if (TARGET_AVX512BW && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512BW && !TARGET_PREFER_AVX256) return V32HImode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V16HImode; @@ -25383,7 +25361,7 @@ ix86_preferred_simd_mode (scalar_mode mode) return V8HImode; case E_SImode: - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) return V16SImode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V8SImode; @@ -25391,7 +25369,7 @@ ix86_preferred_simd_mode (scalar_mode mode) return V4SImode; case E_DImode: - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) return V8DImode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V4DImode; @@ -25405,16 +25383,15 @@ ix86_preferred_simd_mode (scalar_mode mode) { if (TARGET_PREFER_AVX128) return V8HFmode; - else if (TARGET_PREFER_AVX256 || !TARGET_EVEX512) + else if (TARGET_PREFER_AVX256) return V16HFmode; } - if (TARGET_EVEX512) - return V32HFmode; + return V32HFmode; } return word_mode; case E_BFmode: - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) return V32BFmode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V16BFmode; @@ -25422,7 +25399,7 @@ ix86_preferred_simd_mode (scalar_mode mode) return V8BFmode; case E_SFmode: - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) return V16SFmode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V8SFmode; @@ -25430,7 +25407,7 @@ ix86_preferred_simd_mode (scalar_mode mode) return V4SFmode; case E_DFmode: - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) return V8DFmode; else if (TARGET_AVX && !TARGET_PREFER_AVX128) return V4DFmode; @@ -25450,13 +25427,13 @@ ix86_preferred_simd_mode (scalar_mode mode) static unsigned int ix86_autovectorize_vector_modes (vector_modes *modes, bool all) { - if (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256) + if (TARGET_AVX512F && !TARGET_PREFER_AVX256) { modes->safe_push (V64QImode); modes->safe_push (V32QImode); modes->safe_push (V16QImode); } - else if (TARGET_AVX512F && TARGET_EVEX512 && all) + else if (TARGET_AVX512F && all) { modes->safe_push (V32QImode); modes->safe_push (V16QImode); @@ -25494,7 +25471,7 @@ ix86_get_mask_mode (machine_mode data_mode) unsigned elem_size = vector_size / nunits; /* Scalar mask case. */ - if ((TARGET_AVX512F && TARGET_EVEX512 && vector_size == 64) + if ((TARGET_AVX512F && vector_size == 64) || (TARGET_AVX512VL && (vector_size == 32 || vector_size == 16)) /* AVX512FP16 only supports vector comparison to kmask for _Float16. */ @@ -26281,7 +26258,7 @@ ix86_simd_clone_compute_vecsize_and_simdlen (struct cgraph_node *node, { /* If the function isn't exported, we can pick up just one ISA for the clones. */ - if (TARGET_AVX512F && TARGET_EVEX512) + if (TARGET_AVX512F) clonei->vecsize_mangle = 'e'; else if (TARGET_AVX2) clonei->vecsize_mangle = 'd'; @@ -26373,17 +26350,17 @@ ix86_simd_clone_usable (struct cgraph_node *node, machine_mode) return -1; if (!TARGET_AVX) return 0; - return (TARGET_AVX512F && TARGET_EVEX512) ? 3 : TARGET_AVX2 ? 2 : 1; + return TARGET_AVX512F ? 3 : TARGET_AVX2 ? 2 : 1; case 'c': if (!TARGET_AVX) return -1; - return (TARGET_AVX512F && TARGET_EVEX512) ? 2 : TARGET_AVX2 ? 1 : 0; + return TARGET_AVX512F ? 2 : TARGET_AVX2 ? 1 : 0; case 'd': if (!TARGET_AVX2) return -1; - return (TARGET_AVX512F && TARGET_EVEX512) ? 1 : 0; + return TARGET_AVX512F ? 1 : 0; case 'e': - if (!TARGET_AVX512F || !TARGET_EVEX512) + if (!TARGET_AVX512F) return -1; return 0; default: diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 18fa97a9eb0d..5aa056ff553b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -816,7 +816,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ #define BIGGEST_ALIGNMENT \ - (TARGET_IAMCU ? 32 : ((TARGET_AVX512F && TARGET_EVEX512) \ + (TARGET_IAMCU ? 32 : (TARGET_AVX512F \ ? 512 : (TARGET_AVX ? 256 : 128))) /* Maximum stack alignment. */ @@ -1895,7 +1895,7 @@ typedef struct ix86_args { MOVE_MAX_PIECES defaults to MOVE_MAX. */ #define MOVE_MAX \ - ((TARGET_AVX512F && TARGET_EVEX512\ + ((TARGET_AVX512F \ && (ix86_move_max == PVW_AVX512 \ || ix86_store_max == PVW_AVX512)) \ ? 64 \ @@ -1914,7 +1914,7 @@ typedef struct ix86_args { store_by_pieces of 16/32/64 bytes. */ #define STORE_MAX_PIECES \ (TARGET_INTER_UNIT_MOVES_TO_VEC \ - ? ((TARGET_AVX512F && TARGET_EVEX512 && ix86_store_max == PVW_AVX512) \ + ? ((TARGET_AVX512F && ix86_store_max == PVW_AVX512) \ ? 64 \ : ((TARGET_AVX \ && ix86_store_max >= PVW_AVX256) \ @@ -2408,13 +2408,13 @@ constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU - | PTA_CLWB | PTA_EVEX512; + | PTA_CLWB; constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI; constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU - | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512; + | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | PTA_RDPID | PTA_AVX512VPOPCNTDQ; @@ -2444,7 +2444,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD | PTA_UINTR; constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 - | PTA_PREFETCHI; + | PTA_PREFETCHI | PTA_AVX10_1; constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS | PTA_AMX_COMPLEX; constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST; @@ -2456,16 +2456,11 @@ constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; -constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_SKYLAKE | PTA_PKU | PTA_SHA - | PTA_GFNI | PTA_VAES | PTA_VPCLMULQDQ | PTA_RDPID | PTA_PCONFIG - | PTA_WBNOINVD | PTA_CLWB | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_ENQCMD - | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK - | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI - | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_256 - | PTA_AVX10_1 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 - | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 - | PTA_AVX10_2 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 - | PTA_AMX_TRANSPOSE | PTA_MOVRS | PTA_AMX_MOVRS | PTA_USER_MSR; +constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D + | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8 + | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2 + | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_AMX_TRANSPOSE + | PTA_MOVRS | PTA_AMX_MOVRS | PTA_USER_MSR; constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 @@ -2492,7 +2487,7 @@ constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI - | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ | PTA_EVEX512; + | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ; constexpr wide_int_bitmask PTA_ZNVER5 = PTA_ZNVER4 | PTA_AVXVNNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_PREFETCHI; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d67148034aa5..af4f12956251 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -581,12 +581,11 @@ (define_attr "isa" "base,x64,nox64,x64_sse2,x64_sse4,x64_sse4_noavx, x64_avx,x64_avx512bw,x64_avx512dq,apx_ndd,apx_ndd_64, sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx, - avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512, - noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq, - noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni, - avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconvert, - avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl, - vaes_avx512vl,noapx_nf,avx10_2" + avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, + avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl, + avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma, + avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl, + avx_noavx512f,avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2" (const_string "base")) ;; The (bounding maximum) length of an instruction immediate. @@ -956,12 +955,8 @@ (eq_attr "isa" "fma_or_avx512vl") (symbol_ref "TARGET_FMA || TARGET_AVX512VL") (eq_attr "isa" "avx512f") (symbol_ref "TARGET_AVX512F") - (eq_attr "isa" "avx512f_512") - (symbol_ref "TARGET_AVX512F && TARGET_EVEX512") (eq_attr "isa" "noavx512f") (symbol_ref "!TARGET_AVX512F") (eq_attr "isa" "avx512bw") (symbol_ref "TARGET_AVX512BW") - (eq_attr "isa" "avx512bw_512") - (symbol_ref "TARGET_AVX512BW && TARGET_EVEX512") (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW") (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ") (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") @@ -1497,7 +1492,7 @@ [(reg:CC FLAGS_REG) (const_int 0)]) (label_ref (match_operand 3)) (pc)))] - "TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256" + "TARGET_AVX512F && !TARGET_PREFER_AVX256" { ix86_expand_branch (GET_CODE (operands[0]), operands[1], operands[2], operands[3]); @@ -2376,7 +2371,7 @@ (define_expand "movxi" [(set (match_operand:XI 0 "nonimmediate_operand") (match_operand:XI 1 "general_operand"))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "ix86_expand_vector_move (XImode, operands); DONE;") (define_expand "movoi" @@ -2452,7 +2447,7 @@ (define_insn "*movxi_internal_avx512f" [(set (match_operand:XI 0 "nonimmediate_operand" "=v,v ,v ,m") (match_operand:XI 1 "nonimmediate_or_sse_const_operand" " C,BC,vm,v"))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && (register_operand (operands[0], XImode) || register_operand (operands[1], XImode))" { @@ -4416,7 +4411,7 @@ (eq_attr "alternative" "11") (const_string "DI") (eq_attr "alternative" "5") - (cond [(and (match_test "TARGET_AVX512F && TARGET_EVEX512") + (cond [(and (match_test "TARGET_AVX512F") (not (match_test "TARGET_PREFER_AVX256"))) (const_string "V16SF") (match_test "TARGET_AVX") @@ -5484,7 +5479,7 @@ (set_attr "memory" "none") (set (attr "enabled") (if_then_else (eq_attr "alternative" "2") - (symbol_ref "TARGET_AVX512F && TARGET_EVEX512 + (symbol_ref "TARGET_AVX512F && !TARGET_AVX512VL && !TARGET_PREFER_AVX256") (const_string "*")))]) diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 0abf13480f57..c93c0b1bb381 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -36,13 +36,6 @@ HOST_WIDE_INT ix86_isa_flags_explicit Variable HOST_WIDE_INT ix86_isa_flags2_explicit -; Indicate if AVX512 and AVX10.1 are explicitly set no. -Variable -int ix86_no_avx512_explicit = 0 - -Variable -int ix86_no_avx10_1_explicit = 0 - ; Additional target flags Variable int ix86_target_flags @@ -103,14 +96,6 @@ HOST_WIDE_INT x_ix86_isa_flags2_explicit TargetSave HOST_WIDE_INT x_ix86_isa_flags_explicit -;; which flags were passed by the user -TargetSave -HOST_WIDE_INT x_ix86_no_avx512_explicit - -;; which flags were passed by the user -TargetSave -HOST_WIDE_INT x_ix86_no_avx10_1_explicit - ;; whether -mtune was not specified TargetSave unsigned char tune_defaulted @@ -1351,38 +1336,24 @@ mapx-inline-asm-use-gpr32 Target Var(ix86_apx_inline_asm_use_gpr32) Init(0) Enable GPR32 in inline asm when APX_F enabled. -mevex512 -Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Warn(%<-mevex512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) -Support 512 bit vector built-in functions and code generation. - musermsr Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save Support USER_MSR built-in functions and code generation. -mavx10.1-256 -Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and %<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, -and AVX10.1-256 built-in functions and code generation. - mavx10.1 -Target Mask(ISA2_AVX10_1) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and %<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit vector size supported) -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, -and AVX10.1-512 built-in functions and code generation. - -mavx10.1-512 -Target Alias(mavx10.1) +Target Mask(ISA2_AVX10_1) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, -and AVX10.1-512 built-in functions and code generation. +and AVX10.1 built-in functions and code generation. mavx10.2 Target Mask(ISA2_AVX10_2) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, -AVX10.1-512 and AVX10.2 built-in functions and code generation. +AVX10.1 and AVX10.2 built-in functions and code generation. mamx-avx512 Target Mask(ISA2_AMX_AVX512) Var(ix86_isa_flags2) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1-512, -AVX10.2 and AMX-AVX512 built-in functions and code generation. +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1, AVX10.2 and AMX-AVX512 built-in functions and code generation. mamx-tf32 Target Mask(ISA2_AMX_TF32) Var(ix86_isa_flags2) Save diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 0d5a5a10119d..cce524c232e3 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -590,21 +590,12 @@ UrlSuffix(gcc/x86-Options.html#index-mapxf) mapx-inline-asm-use-gpr32 UrlSuffix(gcc/x86-Options.html#index-mapx-inline-asm-use-gpr32) -mevex512 -UrlSuffix(gcc/x86-Options.html#index-mevex512) - musermsr UrlSuffix(gcc/x86-Options.html#index-musermsr) -mavx10.1-256 -UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256) - mavx10.1 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1) -mavx10.1-512 -UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512) - mavx10.2 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2) diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index fbf2dd9fc51e..10ed6a5de56e 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1280,8 +1280,7 @@ (and (match_code "vec_duplicate") (and (match_test "TARGET_AVX512F") (ior (match_test "TARGET_AVX512VL") - (and (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64") - (match_test "TARGET_EVEX512")))) + (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64"))) (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))") (match_test "GET_MODE (XEXP (op, 0)) == GET_MODE_INNER (GET_MODE (op))") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2ed348ced0de..a546479618a5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -279,63 +279,63 @@ ;; All vector modes including V?TImode, used in move patterns. (define_mode_iterator VMOVE - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI - (V4TI "TARGET_AVX512F && TARGET_EVEX512") (V2TI "TARGET_AVX") V1TI - (V32HF "TARGET_AVX512F && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512F && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI + (V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX") V1TI + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512F") (V16BF "TARGET_AVX") V8BF + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) ;; All AVX-512{F,VL} vector modes without HF. Supposed TARGET_AVX512F baseline. (define_mode_iterator V48_AVX512VL - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator V48_256_512_AVX512VL - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") - (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") - (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL")]) + [V16SI (V8SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") + V16SF (V8SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL")]) ;; All AVX-512{F,VL} vector modes. Supposed TARGET_AVX512F baseline. (define_mode_iterator V48H_AVX512VL - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + (V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) ;; 1,2 byte AVX-512{BW,VL} vector modes. Supposed TARGET_AVX512BW baseline. (define_mode_iterator VI12_AVX512VL - [(V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") - (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) + [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) (define_mode_iterator VI12HFBF_AVX512VL - [(V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") - (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") - (V32HF "TARGET_EVEX512") (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL") - (V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") + V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL") + V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX512VL - [(V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) + [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) ;; All vector modes (define_mode_iterator V - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI - (V32HF "TARGET_AVX512F && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512F && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512F") (V16BF "TARGET_AVX") V8BF + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) ;; All 128bit vector modes (define_mode_iterator V_128 @@ -352,32 +352,26 @@ ;; All 512bit vector modes (define_mode_iterator V_512 - [(V64QI "TARGET_EVEX512") (V32HI "TARGET_EVEX512") - (V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512") - (V16SF "TARGET_EVEX512") (V8DF "TARGET_EVEX512") - (V32HF "TARGET_EVEX512") (V32BF "TARGET_EVEX512")]) + [V64QI V32HI V16SI V8DI + V16SF V8DF V32HF V32BF]) ;; All 256bit and 512bit vector modes (define_mode_iterator V_256_512 [V32QI V16HI V16HF V16BF V8SI V4DI V8SF V4DF - (V64QI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512F && TARGET_EVEX512") - (V32HF "TARGET_AVX512F && TARGET_EVEX512") - (V32BF "TARGET_AVX512F && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512")]) + (V64QI "TARGET_AVX512F") (V32HI "TARGET_AVX512F") + (V32HF "TARGET_AVX512F") (V32BF "TARGET_AVX512F") + (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") + (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) ;; All vector float modes (define_mode_iterator VF - [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") + [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) (define_mode_iterator VF1_VF2_AVX512DQ - [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512DQ && TARGET_EVEX512") + [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512DQ") (V4DF "TARGET_AVX512DQ && TARGET_AVX512VL") (V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")]) @@ -386,20 +380,20 @@ (V8DF "TARGET_AVX10_2") V4DF V2DF]) (define_mode_iterator VFH - [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [(V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) (define_mode_iterator VF_BHSD - [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [(V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2") (V32BF "TARGET_AVX10_2") (V16BF "TARGET_AVX10_2") @@ -408,12 +402,12 @@ ;; 128-, 256- and 512-bit float vector modes for bitwise operations (define_mode_iterator VFB - [(V32BF "TARGET_AVX512F && TARGET_EVEX512") + [(V32BF "TARGET_AVX512F") (V16BF "TARGET_AVX") (V8BF "TARGET_SSE2") - (V32HF "TARGET_AVX512F && TARGET_EVEX512") + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") (V8HF "TARGET_SSE2") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) ;; 128- and 256-bit float vector modes @@ -430,44 +424,42 @@ ;; All SFmode vector float modes (define_mode_iterator VF1 - [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF]) + [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF]) (define_mode_iterator VF1_AVX2 - [(V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX2") V4SF]) + [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX2") V4SF]) ;; 128- and 256-bit SF vector modes (define_mode_iterator VF1_128_256 [(V8SF "TARGET_AVX") V4SF]) (define_mode_iterator VF1_128_256VL - [(V8SF "TARGET_EVEX512") (V4SF "TARGET_AVX512VL")]) + [V8SF (V4SF "TARGET_AVX512VL")]) ;; All DFmode vector float modes (define_mode_iterator VF2 - [(V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF]) + [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) (define_mode_iterator VF2_AVX10_2 [(V8DF "TARGET_AVX10_2") V4DF V2DF]) ;; All DFmode & HFmode & BFmode vector float modes (define_mode_iterator VF2HB - [(V32BF "TARGET_AVX10_2") - (V16BF "TARGET_AVX10_2") - (V8BF "TARGET_AVX10_2") - (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [(V32BF "TARGET_AVX10_2") (V16BF "TARGET_AVX10_2") + (V8BF "TARGET_AVX10_2") (V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF]) + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) ;; 128- and 256-bit DF vector modes (define_mode_iterator VF2_128_256 [(V4DF "TARGET_AVX") V2DF]) (define_mode_iterator VF2_512_256 - [(V8DF "TARGET_AVX512F && TARGET_EVEX512") V4DF]) + [(V8DF "TARGET_AVX512F") V4DF]) (define_mode_iterator VF2_512_256VL - [(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL")]) + [V8DF (V4DF "TARGET_AVX512VL")]) ;; All 128bit vector SF/DF modes (define_mode_iterator VF_128 @@ -484,31 +476,28 @@ ;; All 512bit vector float modes (define_mode_iterator VF_512 - [(V16SF "TARGET_EVEX512") (V8DF "TARGET_EVEX512")]) + [V16SF V8DF]) ;; All 512bit vector float modes for bitwise operations (define_mode_iterator VFB_512 - [(V32BF "TARGET_EVEX512") - (V32HF "TARGET_EVEX512") - (V16SF "TARGET_EVEX512") - (V8DF "TARGET_EVEX512")]) + [V32BF V32HF V16SF V8DF]) (define_mode_iterator V24F_128 [V4SF V8HF V8BF]) (define_mode_iterator VI48_AVX512VL - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI1248_AVX512VLBW - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") (V16QI "TARGET_AVX512VL && TARGET_AVX512BW") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") (V8HI "TARGET_AVX512VL && TARGET_AVX512BW") - (V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI1248_AVX10_2 [(V64QI "TARGET_AVX10_2") V32QI V16QI @@ -517,15 +506,15 @@ (V8DI "TARGET_AVX10_2") V4DI V2DI]) (define_mode_iterator VF_AVX512VL - [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VFH_AVX512VL - [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [(V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator V48_AVX512VL_4 [(V4SF "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") @@ -543,29 +532,28 @@ (V8DF "TARGET_AVX10_2") V4DF V2DF]) (define_mode_iterator VF2_AVX512VL - [(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VF1_AVX512VL - [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")]) + [V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")]) (define_mode_iterator VF1_AVX512BW - [(V16SF "TARGET_AVX512BW && TARGET_EVEX512") (V8SF "TARGET_AVX2") V4SF]) + [(V16SF "TARGET_AVX512BW") (V8SF "TARGET_AVX2") V4SF]) (define_mode_iterator VF1_AVX10_2 [(V16SF "TARGET_AVX10_2") V8SF V4SF]) (define_mode_iterator VHFBF - [(V32HF "TARGET_EVEX512") V16HF V8HF - (V32BF "TARGET_EVEX512") V16BF V8BF]) + [V32HF V16HF V8HF V32BF V16BF V8BF]) (define_mode_iterator VHFBF_256 [V16HF V16BF]) (define_mode_iterator VHFBF_128 [V8HF V8BF]) (define_mode_iterator VHF_AVX512VL - [(V32HF "TARGET_EVEX512") (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL")]) + [V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL")]) (define_mode_iterator VHFBF_AVX512VL - [(V32HF "TARGET_EVEX512") (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL") - (V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + [V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL") + V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) (define_mode_iterator VHF_AVX10_2 [(V32HF "TARGET_AVX10_2") V16HF V8HF]) @@ -575,35 +563,32 @@ ;; All vector integer modes (define_mode_iterator VI - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI + [(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") + (V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX") V8HI (V8SI "TARGET_AVX") V4SI (V4DI "TARGET_AVX") V2DI]) ;; All vector integer and HF modes (define_mode_iterator VIHFBF - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V8SI "TARGET_AVX") V4SI - (V4DI "TARGET_AVX") V2DI - (V32HF "TARGET_AVX512BW && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512BW && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF]) + [(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") + (V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX") V8HI + (V8SI "TARGET_AVX") V4SI (V4DI "TARGET_AVX") V2DI + (V32HF "TARGET_AVX512BW") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512BW") (V16BF "TARGET_AVX") V8BF]) (define_mode_iterator VI_AVX2 - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX2") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI_AVX_AVX512F - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) ;; All QImode vector integer modes (define_mode_iterator VI1 @@ -621,51 +606,51 @@ (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")]) (define_mode_iterator VI8 - [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI]) + [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) (define_mode_iterator VI8_AVX10_2 [(V8DI "TARGET_AVX10_2") V4DI V2DI]) (define_mode_iterator VI8_FVL - [(V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI (V2DI "TARGET_AVX512VL")]) + [(V8DI "TARGET_AVX512F") V4DI (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_AVX512VL - [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_256_512 - [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL")]) + [V8DI (V4DI "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX2 [(V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI1_AVX512 - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI1_AVX512F - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI]) (define_mode_iterator VI1_AVX512VNNI - [(V64QI "TARGET_AVX512VNNI && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) + [(V64QI "TARGET_AVX512VNNI") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI1_AVX512VNNIBW - [(V64QI "(TARGET_AVX512BW || TARGET_AVX512VNNI) && TARGET_EVEX512") + [(V64QI "TARGET_AVX512BW || TARGET_AVX512VNNI") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI12_256_512_AVX512VL - [(V64QI "TARGET_EVEX512") (V32QI "TARGET_AVX512VL") - (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL")]) + [V64QI (V32QI "TARGET_AVX512VL") + V32HI (V16HI "TARGET_AVX512VL")]) (define_mode_iterator VI2_AVX2 [(V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI2_AVX2_AVX512BW - [(V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI]) + [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI2_AVX512F - [(V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI]) + [(V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI2_AVX512VNNIBW - [(V32HI "(TARGET_AVX512BW || TARGET_AVX512VNNI) && TARGET_EVEX512") + [(V32HI "TARGET_AVX512BW || TARGET_AVX512VNNI") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI2_AVX10_2 @@ -678,65 +663,64 @@ [(V8SI "TARGET_AVX2") V4SI]) (define_mode_iterator VI4_AVX512F - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX2") V4SI]) + [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI]) (define_mode_iterator VI4_AVX512VL - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) (define_mode_iterator VI4_AVX10_2 [(V16SI "TARGET_AVX10_2") V8SI V4SI]) (define_mode_iterator VI48_AVX512F_AVX512VL - [V4SI V8SI (V16SI "TARGET_AVX512F && TARGET_EVEX512") + [V4SI V8SI (V16SI "TARGET_AVX512F") (V2DI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") - (V8DI "TARGET_AVX512F && TARGET_EVEX512")]) + (V8DI "TARGET_AVX512F")]) (define_mode_iterator VI2_AVX512VL - [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") (V32HI "TARGET_EVEX512")]) + [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI]) (define_mode_iterator VI2HFBF_AVX512VL - [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") (V32HI "TARGET_EVEX512") - (V8HF "TARGET_AVX512VL") (V16HF "TARGET_AVX512VL") (V32HF "TARGET_EVEX512") - (V8BF "TARGET_AVX512VL") (V16BF "TARGET_AVX512VL") (V32BF "TARGET_EVEX512")]) + [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI + (V8HF "TARGET_AVX512VL") (V16HF "TARGET_AVX512VL") V32HF + (V8BF "TARGET_AVX512VL") (V16BF "TARGET_AVX512VL") V32BF]) (define_mode_iterator VI2H_AVX512VL - [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") (V32HI "TARGET_EVEX512") - (V8SI "TARGET_AVX512VL") (V16SI "TARGET_EVEX512") - (V8DI "TARGET_EVEX512")]) + [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI + (V8SI "TARGET_AVX512VL") V16SI V8DI]) (define_mode_iterator VI1_AVX512VL_F - [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F && TARGET_EVEX512")]) + [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")]) (define_mode_iterator VI8_AVX2_AVX512BW - [(V8DI "TARGET_AVX512BW && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) + [(V8DI "TARGET_AVX512BW") (V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI8_AVX2 [(V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI8_AVX2_AVX512F - [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) + [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI8_AVX_AVX512F - [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX")]) + [(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX")]) (define_mode_iterator VI4_128_8_256 [V4SI V4DI]) ;; All V8D* modes (define_mode_iterator V8FI - [(V8DF "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [V8DF V8DI]) ;; All V16S* modes (define_mode_iterator V16FI - [(V16SF "TARGET_EVEX512") (V16SI "TARGET_EVEX512")]) + [V16SF V16SI]) ;; ??? We should probably use TImode instead. (define_mode_iterator VIMAX_AVX2_AVX512BW - [(V4TI "TARGET_AVX512BW && TARGET_EVEX512") (V2TI "TARGET_AVX2") V1TI]) + [(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") V1TI]) ;; Suppose TARGET_AVX512BW as baseline (define_mode_iterator VIMAX_AVX512VL - [(V4TI "TARGET_EVEX512") (V2TI "TARGET_AVX512VL") (V1TI "TARGET_AVX512VL")]) + [V4TI (V2TI "TARGET_AVX512VL") (V1TI "TARGET_AVX512VL")]) (define_mode_iterator VIMAX_AVX2 [(V2TI "TARGET_AVX2") V1TI]) @@ -746,17 +730,17 @@ (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI12_AVX2_AVX512BW - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI24_AVX2 [(V16HI "TARGET_AVX2") V8HI (V8SI "TARGET_AVX2") V4SI]) (define_mode_iterator VI124_AVX2_24_AVX512F_1_AVX512BW - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX2") V4SI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX2") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI]) (define_mode_iterator VI124_AVX2 [(V32QI "TARGET_AVX2") V16QI @@ -764,17 +748,17 @@ (V8SI "TARGET_AVX2") V4SI]) (define_mode_iterator VI248_AVX512VL - [(V32HI "TARGET_EVEX512") (V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512") + [V32HI V16SI V8DI (V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI248_AVX512VLBW - [(V32HI "TARGET_AVX512BW && TARGET_EVEX512") + [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") (V8HI "TARGET_AVX512VL && TARGET_AVX512BW") - (V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI48_AVX2 [(V8SI "TARGET_AVX2") V4SI @@ -786,17 +770,16 @@ (V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI248_AVX2_8_AVX512F_24_AVX512BW - [(V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI - (V16SI "TARGET_AVX512BW && TARGET_EVEX512") (V8SI "TARGET_AVX2") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) + [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI + (V16SI "TARGET_AVX512BW") (V8SI "TARGET_AVX2") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VI248_AVX512BW - [(V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16SI "TARGET_EVEX512") - (V8DI "TARGET_EVEX512")]) + [(V32HI "TARGET_AVX512BW") V16SI V8DI]) (define_mode_iterator VI248_AVX512BW_AVX512VL - [(V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V4DI "TARGET_AVX512VL") (V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [(V32HI "TARGET_AVX512BW") + (V4DI "TARGET_AVX512VL") V16SI V8DI]) ;; Suppose TARGET_AVX512VL as baseline (define_mode_iterator VI248_AVX512BW_1 @@ -810,16 +793,16 @@ V4DI V2DI]) (define_mode_iterator VI48_AVX512F - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") V8SI V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI V2DI]) + [(V16SI "TARGET_AVX512F") V8SI V4SI + (V8DI "TARGET_AVX512F") V4DI V2DI]) (define_mode_iterator VI48_AVX_AVX512F - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI]) + [(V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI]) (define_mode_iterator VI12_AVX_AVX512F - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI]) (define_mode_iterator V48_128_256 [V4SF V2DF @@ -960,10 +943,10 @@ (define_mode_iterator VI248_128 [V8HI V4SI V2DI]) (define_mode_iterator VI248_256 [V16HI V8SI V4DI]) (define_mode_iterator VI248_512 - [(V32HI "TARGET_EVEX512") (V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [V32HI V16SI V8DI]) (define_mode_iterator VI48_128 [V4SI V2DI]) (define_mode_iterator VI148_512 - [(V64QI "TARGET_EVEX512") (V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [V64QI V16SI V8DI]) (define_mode_iterator VI148_256 [V32QI V8SI V4DI]) (define_mode_iterator VI148_128 [V16QI V4SI V2DI]) @@ -971,75 +954,62 @@ (define_mode_iterator VI124_256 [V32QI V16HI V8SI]) (define_mode_iterator VI124_256_AVX512F_AVX512BW [V32QI V16HI V8SI - (V64QI "TARGET_AVX512BW && TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512")]) + (V64QI "TARGET_AVX512BW") (V32HI "TARGET_AVX512BW") + (V16SI "TARGET_AVX512F")]) (define_mode_iterator VI48_256 [V8SI V4DI]) (define_mode_iterator VI48_512 - [(V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [V16SI V8DI]) (define_mode_iterator VI4_256_8_512 [V8SI V8DI]) (define_mode_iterator VI_AVX512BW - [(V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V64QI "TARGET_AVX512BW && TARGET_EVEX512")]) + [V16SI V8DI + (V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512BW")]) (define_mode_iterator VIHFBF_AVX512BW - [(V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V64QI "TARGET_AVX512BW && TARGET_EVEX512") - (V32HF "TARGET_AVX512BW && TARGET_EVEX512") - (V32BF "TARGET_AVX512BW && TARGET_EVEX512")]) + [V16SI V8DI + (V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512BW") + (V32HF "TARGET_AVX512BW") (V32BF "TARGET_AVX512BW")]) ;; Int-float size matches (define_mode_iterator VI2F_256_512 - [V16HI (V32HI "TARGET_EVEX512") - V16HF (V32HF "TARGET_EVEX512") - V16BF (V32BF "TARGET_EVEX512")]) + [V16HI V32HI V16HF V32HF V16BF V32BF]) (define_mode_iterator VI4F_128 [V4SI V4SF]) (define_mode_iterator VI8F_128 [V2DI V2DF]) (define_mode_iterator VI4F_256 [V8SI V8SF]) (define_mode_iterator VI8F_256 [V4DI V4DF]) (define_mode_iterator VI4F_256_512 - [V8SI V8SF - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512")]) + [V8SI V8SF (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")]) (define_mode_iterator VI48F_256_512 [V8SI V8SF - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) + (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F") + (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) (define_mode_iterator VF48H_AVX512VL - [(V8DF "TARGET_EVEX512") (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) + [V8DF V16SF (V8SF "TARGET_AVX512VL")]) (define_mode_iterator VF48_128 [V2DF V4SF]) (define_mode_iterator VI48F - [(V16SI "TARGET_EVEX512") (V16SF "TARGET_EVEX512") - (V8DI "TARGET_EVEX512") (V8DF "TARGET_EVEX512") + [V16SI V16SF V8DI V8DF (V8SI "TARGET_AVX512VL") (V8SF "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_mode_iterator VI12_VI48F_AVX512VL - [(V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") + [(V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V8DI "TARGET_AVX512F") (V8DF "TARGET_AVX512F") (V8SI "TARGET_AVX512VL") (V8SF "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL") - (V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") - (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) + V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) (define_mode_iterator VI48F_256 [V8SI V8SF V4DI V4DF]) (define_mode_iterator V8_128 [V8HI V8HF V8BF]) (define_mode_iterator V16_256 [V16HI V16HF V16BF]) (define_mode_iterator V32_512 - [(V32HI "TARGET_EVEX512") (V32HF "TARGET_EVEX512") (V32BF "TARGET_EVEX512")]) + [V32HI V32HF V32BF]) ;; Mapping from float mode to required SSE level (define_mode_attr sse @@ -1451,7 +1421,7 @@ ;; Mix-n-match (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF]) (define_mode_iterator AVX512MODE2P - [(V16SI "TARGET_EVEX512") (V16SF "TARGET_EVEX512") (V8DF "TARGET_EVEX512")]) + [V16SI V16SF V8DF]) ;; Mapping for dbpsabbw modes (define_mode_attr dbpsadbwmode @@ -2059,11 +2029,9 @@ (define_mode_iterator STORENT_MODE [(DI "TARGET_SSE2 && TARGET_64BIT") (SI "TARGET_SSE2") (SF "TARGET_SSE4A") (DF "TARGET_SSE4A") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V4DI "TARGET_AVX") (V2DI "TARGET_SSE2") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") (V2DI "TARGET_SSE2") + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) (define_expand "storent" [(set (match_operand:STORENT_MODE 0 "memory_operand") @@ -3907,15 +3875,12 @@ (define_mode_iterator REDUC_PLUS_MODE [(V4DF "TARGET_AVX") (V8SF "TARGET_AVX") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V32HF "TARGET_AVX512FP16 && TARGET_AVX512VL && TARGET_EVEX512") + (V8DF "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V32HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V32QI "TARGET_AVX") (V16HI "TARGET_AVX") (V8SI "TARGET_AVX") (V4DI "TARGET_AVX") - (V64QI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512F && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512")]) + (V64QI "TARGET_AVX512F") (V32HI "TARGET_AVX512F") + (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")]) (define_expand "reduc_plus_scal_" [(plus:REDUC_PLUS_MODE @@ -3958,13 +3923,11 @@ (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") (V8SF "TARGET_AVX") (V4DF "TARGET_AVX") - (V64QI "TARGET_AVX512BW && TARGET_EVEX512") - (V32HF "TARGET_AVX512FP16 && TARGET_AVX512VL && TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512")]) + (V64QI "TARGET_AVX512BW") + (V32HF "TARGET_AVX512FP16 && TARGET_AVX512VL") + (V32HI "TARGET_AVX512BW") (V16SI "TARGET_AVX512F") + (V8DI "TARGET_AVX512F") (V16SF "TARGET_AVX512F") + (V8DF "TARGET_AVX512F")]) (define_expand "reduc__scal_" [(smaxmin:REDUC_SMINMAX_MODE @@ -4073,10 +4036,8 @@ (define_mode_iterator REDUC_ANY_LOGIC_MODE [(V32QI "TARGET_AVX") (V16HI "TARGET_AVX") (V8SI "TARGET_AVX") (V4DI "TARGET_AVX") - (V64QI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512F && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512")]) + (V64QI "TARGET_AVX512F") (V32HI "TARGET_AVX512F") + (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")]) (define_expand "reduc__scal_" [(any_logic:REDUC_ANY_LOGIC_MODE @@ -5649,7 +5610,7 @@ output_asm_insn (buf, operands); return ""; } - [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512") + [(set_attr "isa" "noavx,avx,avx512vl,avx512f") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex,evex,evex") (set (attr "mode") @@ -5706,7 +5667,7 @@ output_asm_insn (buf, operands); return ""; } - [(set_attr "isa" "noavx,avx_noavx512vl,avx512vl,avx512f_512") + [(set_attr "isa" "noavx,avx_noavx512f,avx512vl,avx512f") (set_attr "addr" "*,gpr16,*,*") (set_attr "type" "sselog") (set (attr "prefix_data16") @@ -5779,7 +5740,7 @@ output_asm_insn (buf, operands); return ""; } - [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512") + [(set_attr "isa" "noavx,avx,avx512vl,avx512f") (set_attr "type" "sselog") (set_attr "prefix" "orig,vex,evex,evex") (set (attr "mode") @@ -5841,7 +5802,7 @@ output_asm_insn (buf, operands); return ""; } - [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512") + [(set_attr "isa" "noavx,avx,avx512vl,avx512f") (set_attr "type" "sselog") (set (attr "prefix_data16") (if_then_else @@ -5887,15 +5848,10 @@ (V2DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") (V8SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") (V4DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (HF "TARGET_AVX512FP16") - (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") - (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") - (V8BF "TARGET_AVX10_2") - (V16BF "TARGET_AVX10_2") - (V32BF "TARGET_AVX10_2")]) + (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F") + (HF "TARGET_AVX512FP16") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") + (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V32HF "TARGET_AVX512FP16") + (V8BF "TARGET_AVX10_2") (V16BF "TARGET_AVX10_2") (V32BF "TARGET_AVX10_2")]) (define_expand "fma4" [(set (match_operand:FMAMODEM 0 "register_operand") @@ -5933,8 +5889,7 @@ (V2DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") (V8SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") (V4DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512")]) + (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F")]) (define_mode_iterator FMAMODE [SF DF V4SF V2DF V8SF V4DF]) @@ -6004,14 +5959,12 @@ ;; Suppose AVX-512F as baseline (define_mode_iterator VFH_SF_AVX512VL - [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") + [(V32HF "TARGET_AVX512FP16") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (HF "TARGET_AVX512FP16") - SF (V16SF "TARGET_EVEX512") - (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") - DF (V8DF "TARGET_EVEX512") - (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) + SF V16SF (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") + DF V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) (define_insn "fma_fmadd_" [(set (match_operand:VFH_SF_AVX512VL 0 "register_operand" "=v,v,v") @@ -8759,7 +8712,7 @@ (unspec:V16SI [(match_operand:V16SF 1 "" "")] UNSPEC_FIX_NOTRUNC))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -8827,7 +8780,7 @@ (unspec:V16SI [(match_operand:V16SF 1 "" "")] UNSPEC_VCVTT_U))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvttps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -8837,7 +8790,7 @@ [(set (match_operand:V16SI 0 "register_operand" "=v") (any_fix:V16SI (match_operand:V16SF 1 "" "")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvttps2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -9425,7 +9378,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtdq2pd\t{%t1, %0|%0, %t1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -9461,7 +9414,7 @@ (unspec:V8SI [(match_operand:V8DF 1 "" "")] UNSPEC_FIX_NOTRUNC))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -9620,7 +9573,7 @@ (unspec:V8SI [(match_operand:V8DF 1 "" "")] UNSPEC_VCVTT_U))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvttpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -9630,7 +9583,7 @@ [(set (match_operand:V8SI 0 "register_operand" "=v") (any_fix:V8SI (match_operand:V8DF 1 "" "")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvttpd2dq\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -10146,7 +10099,7 @@ [(set (match_operand:V8SF 0 "register_operand" "=v") (float_truncate:V8SF (match_operand:V8DF 1 "" "")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtpd2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -10308,7 +10261,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtps2pd\t{%t1, %0|%0, %t1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -10514,7 +10467,7 @@ (set (match_operand:V8DF 0 "register_operand") (float_extend:V8DF (match_dup 2)))] -"TARGET_AVX512F && TARGET_EVEX512" +"TARGET_AVX512F" "operands[2] = gen_reg_rtx (V8SFmode);") (define_expand "vec_unpacks_lo_v4sf" @@ -10652,7 +10605,7 @@ (set (match_operand:V8DF 0 "register_operand") (float:V8DF (match_dup 2)))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "operands[2] = gen_reg_rtx (V8SImode);") (define_expand "vec_unpacks_float_lo_v16si" @@ -10664,7 +10617,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_expand "vec_unpacku_float_hi_v4si" [(set (match_dup 5) @@ -10760,7 +10713,7 @@ (define_expand "vec_unpacku_float_hi_v16si" [(match_operand:V8DF 0 "register_operand") (match_operand:V16SI 1 "register_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { REAL_VALUE_TYPE TWO32r; rtx k, x, tmp[4]; @@ -10809,7 +10762,7 @@ (define_expand "vec_unpacku_float_lo_v16si" [(match_operand:V8DF 0 "register_operand") (match_operand:V16SI 1 "nonimmediate_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { REAL_VALUE_TYPE TWO32r; rtx k, x, tmp[3]; @@ -10903,7 +10856,7 @@ [(match_operand:V16SI 0 "register_operand") (match_operand:V8DF 1 "nonimmediate_operand") (match_operand:V8DF 2 "nonimmediate_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { rtx r1, r2; @@ -11018,7 +10971,7 @@ [(match_operand:V16SI 0 "register_operand") (match_operand:V8DF 1 "nonimmediate_operand") (match_operand:V8DF 2 "nonimmediate_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { rtx r1, r2; @@ -11211,7 +11164,7 @@ (const_int 11) (const_int 27) (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vunpckhps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -11299,7 +11252,7 @@ (const_int 9) (const_int 25) (const_int 12) (const_int 28) (const_int 13) (const_int 29)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vunpcklps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -11439,7 +11392,7 @@ (const_int 11) (const_int 11) (const_int 13) (const_int 13) (const_int 15) (const_int 15)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vmovshdup\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "prefix" "evex") @@ -11492,7 +11445,7 @@ (const_int 10) (const_int 10) (const_int 12) (const_int 12) (const_int 14) (const_int 14)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vmovsldup\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "prefix" "evex") @@ -12452,9 +12405,7 @@ (V8SF "32x4") (V8SI "32x4") (V4DF "64x2") (V4DI "64x2")]) (define_mode_iterator AVX512_VEC - [(V8DF "TARGET_AVX512DQ && TARGET_EVEX512") - (V8DI "TARGET_AVX512DQ && TARGET_EVEX512") - (V16SF "TARGET_EVEX512") (V16SI "TARGET_EVEX512")]) + [(V8DF "TARGET_AVX512DQ") (V8DI "TARGET_AVX512DQ") V16SF V16SI]) (define_expand "_vextract_mask" [(match_operand: 0 "nonimmediate_operand") @@ -12623,9 +12574,7 @@ [(V16SF "32x8") (V16SI "32x8") (V8DF "64x4") (V8DI "64x4")]) (define_mode_iterator AVX512_VEC_2 - [(V16SF "TARGET_AVX512DQ && TARGET_EVEX512") - (V16SI "TARGET_AVX512DQ && TARGET_EVEX512") - (V8DF "TARGET_EVEX512") (V8DI "TARGET_EVEX512")]) + [(V16SF "TARGET_AVX512DQ") (V16SI "TARGET_AVX512DQ") V8DF V8DI]) (define_expand "_vextract_mask" [(match_operand: 0 "nonimmediate_operand") @@ -13186,7 +13135,7 @@ (const_int 26) (const_int 27) (const_int 28) (const_int 29) (const_int 30) (const_int 31)])))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))" { if (TARGET_AVX512VL @@ -13235,7 +13184,7 @@ (const_int 58) (const_int 59) (const_int 60) (const_int 61) (const_int 62) (const_int 63)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vextracti64x4\t{$0x1, %1, %0|%0, %1, 0x1}" [(set_attr "type" "sselog1") (set_attr "length_immediate" "1") @@ -13333,15 +13282,15 @@ ;; Modes handled by vec_extract patterns. (define_mode_iterator VEC_EXTRACT_MODE - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI - (V32HF "TARGET_AVX512BW && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512BW && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF - (V4TI "TARGET_AVX512F && TARGET_EVEX512") (V2TI "TARGET_AVX")]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI + (V32HF "TARGET_AVX512BW") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512BW") (V16BF "TARGET_AVX") V8BF + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF + (V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX")]) (define_expand "vec_extract" [(match_operand: 0 "register_operand") @@ -13383,7 +13332,7 @@ (const_int 3) (const_int 11) (const_int 5) (const_int 13) (const_int 7) (const_int 15)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vunpckhpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -13497,7 +13446,7 @@ (const_int 2) (const_int 10) (const_int 4) (const_int 12) (const_int 6) (const_int 14)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vmovddup\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") (set_attr "prefix" "evex") @@ -13513,7 +13462,7 @@ (const_int 2) (const_int 10) (const_int 4) (const_int 12) (const_int 6) (const_int 14)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vunpcklpd\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -13725,7 +13674,7 @@ (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) /* Disallow embeded broadcast for vector HFmode since it's not real AVX512FP16 instruction. */ && (GET_MODE_SIZE (GET_MODE_INNER (mode)) >= 4 @@ -13807,7 +13756,7 @@ [(set (match_operand:V 0 "register_operand") (match_operand:V 1 "ternlog_operand"))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && ix86_pre_reload_split ()" "#" "&& 1" @@ -13837,7 +13786,7 @@ (match_operand:V 3 "regmem_or_bitnot_regmem_operand") (match_operand:V 4 "regmem_or_bitnot_regmem_operand"))))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && ix86_pre_reload_split () && (rtx_equal_p (STRIP_UNARY (operands[1]), STRIP_UNARY (operands[4])) @@ -13922,7 +13871,7 @@ (match_operand:V 3 "regmem_or_bitnot_regmem_operand")) (match_operand:V 4 "regmem_or_bitnot_regmem_operand")))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && ix86_pre_reload_split () && (rtx_equal_p (STRIP_UNARY (operands[1]), STRIP_UNARY (operands[4])) @@ -14006,7 +13955,7 @@ (match_operand:V 2 "regmem_or_bitnot_regmem_operand")) (match_operand:V 3 "regmem_or_bitnot_regmem_operand")))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && ix86_pre_reload_split ()" "#" "&& 1" @@ -14156,7 +14105,7 @@ (match_operand:SI 3 "const_0_to_255_operand") (match_operand:V16SF 4 "register_operand") (match_operand:HI 5 "register_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { int mask = INTVAL (operands[3]); emit_insn (gen_avx512f_shufps512_1_mask (operands[0], operands[1], operands[2], @@ -14343,7 +14292,7 @@ (match_operand 16 "const_12_to_15_operand") (match_operand 17 "const_28_to_31_operand") (match_operand 18 "const_28_to_31_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4) && INTVAL (operands[4]) == (INTVAL (operands[8]) - 4) && INTVAL (operands[5]) == (INTVAL (operands[9]) - 4) @@ -14378,7 +14327,7 @@ (match_operand:SI 3 "const_0_to_255_operand") (match_operand:V8DF 4 "register_operand") (match_operand:QI 5 "register_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { int mask = INTVAL (operands[3]); emit_insn (gen_avx512f_shufpd512_1_mask (operands[0], operands[1], operands[2], @@ -14408,7 +14357,7 @@ (match_operand 8 "const_12_to_13_operand") (match_operand 9 "const_6_to_7_operand") (match_operand 10 "const_14_to_15_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { int mask; mask = INTVAL (operands[3]); @@ -14540,7 +14489,7 @@ (const_int 3) (const_int 11) (const_int 5) (const_int 13) (const_int 7) (const_int 15)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -14590,7 +14539,7 @@ (const_int 2) (const_int 10) (const_int 4) (const_int 12) (const_int 6) (const_int 14)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -14956,7 +14905,7 @@ (set_attr "mode" "V2DF,DF,V8DF") (set (attr "enabled") (cond [(eq_attr "alternative" "2") - (symbol_ref "TARGET_AVX512F && TARGET_EVEX512 + (symbol_ref "TARGET_AVX512F && !TARGET_AVX512VL && !TARGET_PREFER_AVX256") (match_test "") (const_string "*") @@ -15041,13 +14990,13 @@ [(set (match_operand:PMOV_DST_MODE_1 0 "nonimmediate_operand") (truncate:PMOV_DST_MODE_1 (match_operand: 1 "register_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_insn "*avx512f_2" [(set (match_operand:PMOV_DST_MODE_1 0 "nonimmediate_operand" "=v,m") (any_truncate:PMOV_DST_MODE_1 (match_operand: 1 "register_operand" "v,v")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmov\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "none,store") @@ -15069,7 +15018,7 @@ (const_int 10) (const_int 11) (const_int 12) (const_int 13) (const_int 14) (const_int 15)])))] - "TARGET_AVX512BW && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512BW && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -15094,7 +15043,7 @@ (const_int 10) (const_int 11) (const_int 12) (const_int 13) (const_int 14) (const_int 15)])))] - "TARGET_AVX512BW && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512BW && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -15178,7 +15127,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])))] - "TARGET_AVX512F && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512F && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -15194,7 +15143,7 @@ (match_operand: 1 "register_operand" "v,v")) (match_operand:PMOV_DST_MODE_1 2 "nonimm_or_0_operand" "0C,0") (match_operand: 3 "register_operand" "Yk,Yk")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmov\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "none,store") @@ -15208,19 +15157,19 @@ (match_operand: 1 "register_operand")) (match_dup 0) (match_operand: 2 "register_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_expand "truncv32hiv32qi2" [(set (match_operand:V32QI 0 "nonimmediate_operand") (truncate:V32QI (match_operand:V32HI 1 "register_operand")))] - "TARGET_AVX512BW && TARGET_EVEX512") + "TARGET_AVX512BW") (define_insn "avx512bw_v32hiv32qi2" [(set (match_operand:V32QI 0 "nonimmediate_operand" "=v,m") (any_truncate:V32QI (match_operand:V32HI 1 "register_operand" "v,v")))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpmovwb\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "none,store") @@ -15250,7 +15199,7 @@ (const_int 26) (const_int 27) (const_int 28) (const_int 29) (const_int 30) (const_int 31)])))] - "TARGET_AVX512VBMI && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512VBMI && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -15266,7 +15215,7 @@ (match_operand:V32HI 1 "register_operand" "v,v")) (match_operand:V32QI 2 "nonimm_or_0_operand" "0C,0") (match_operand:SI 3 "register_operand" "Yk,Yk")))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpmovwb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "none,store") @@ -15280,7 +15229,7 @@ (match_operand:V32HI 1 "register_operand")) (match_dup 0) (match_operand:SI 2 "register_operand")))] - "TARGET_AVX512BW && TARGET_EVEX512") + "TARGET_AVX512BW") (define_mode_iterator PMOV_DST_MODE_2 [V4SI V8HI (V16QI "TARGET_AVX512BW")]) @@ -16138,7 +16087,7 @@ [(set (match_operand:V8QI 0 "register_operand") (truncate:V8QI (match_operand:V8DI 1 "register_operand")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { rtx op0 = gen_reg_rtx (V16QImode); @@ -16158,7 +16107,7 @@ (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovqb\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -16168,7 +16117,7 @@ [(set (match_operand:V8QI 0 "memory_operand" "=m") (any_truncate:V8QI (match_operand:V8DI 1 "register_operand" "v")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovqb\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "store") @@ -16180,7 +16129,7 @@ (subreg:DI (any_truncate:V8QI (match_operand:V8DI 1 "register_operand")) 0))] - "TARGET_AVX512F && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512F && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -16204,7 +16153,7 @@ (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovqb\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -16225,7 +16174,7 @@ (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0) (const_int 0)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovqb\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -16238,7 +16187,7 @@ (match_operand:V8DI 1 "register_operand" "v")) (match_dup 0) (match_operand:QI 2 "register_operand" "Yk")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovqb\t{%1, %0%{%2%}|%0%{%2%}, %1}" [(set_attr "type" "ssemov") (set_attr "memory" "store") @@ -16250,7 +16199,7 @@ (any_truncate:V8QI (match_operand:V8DI 1 "register_operand")) (match_operand:QI 2 "register_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { operands[0] = adjust_address_nv (operands[0], V8QImode, 0); emit_insn (gen_avx512f_v8div16qi2_mask_store_1 (operands[0], @@ -16507,7 +16456,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (MULT, V16SImode, operands);") (define_insn "*vec_widen_umult_even_v16si" @@ -16527,7 +16476,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuludq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") @@ -16623,7 +16572,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (MULT, V16SImode, operands);") (define_insn "*vec_widen_smult_even_v16si" @@ -16643,7 +16592,7 @@ (const_int 4) (const_int 6) (const_int 8) (const_int 10) (const_int 12) (const_int 14)])))))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") @@ -17045,7 +16994,7 @@ "TARGET_SSE2" { /* Try with vnni instructions. */ - if (( == 64 && TARGET_AVX512VNNI && TARGET_EVEX512) + if (( == 64 && TARGET_AVX512VNNI) || ( < 64 && ((TARGET_AVX512VNNI && TARGET_AVX512VL) || TARGET_AVXVNNI))) { @@ -17138,7 +17087,7 @@ (match_operand:V64QI 1 "register_operand") (match_operand:V64QI 2 "nonimmediate_operand") (match_operand:V16SI 3 "nonimmediate_operand")] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" { rtx t1 = gen_reg_rtx (V8DImode); rtx t2 = gen_reg_rtx (V16SImode); @@ -18376,13 +18325,10 @@ (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") (V8SF "TARGET_AVX2") (V4DF "TARGET_AVX2") (V16HF "TARGET_AVX512FP16") - (V16SF "TARGET_AVX512F && TARGET_EVEX512") - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (V16SI "TARGET_AVX512F && TARGET_EVEX512") - (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") - (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") - (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")]) + (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F") + (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") + (V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512VBMI") + (V32HF "TARGET_AVX512FP16")]) (define_expand "vec_perm" [(match_operand:VEC_PERM_AVX2 0 "register_operand") @@ -18409,7 +18355,7 @@ { operands[2] = CONSTM1_RTX (mode); - if (!TARGET_AVX512F || (!TARGET_AVX512VL && !TARGET_EVEX512)) + if (!TARGET_AVX512F) operands[2] = force_reg (mode, operands[2]); }) @@ -18418,7 +18364,6 @@ (xor:VI (match_operand:VI 1 "bcst_vector_operand" " 0, m,Br") (match_operand:VI 2 "vector_all_ones_operand" "BC,BC,BC")))] "TARGET_AVX512F - && ( == 64 || TARGET_AVX512VL || TARGET_EVEX512) && (! || mode == SImode || mode == DImode)" @@ -18485,7 +18430,7 @@ (match_operand:VI 2 "vector_all_ones_operand" "BC,BC,BC"))) (unspec [(match_operand:VI 3 "register_operand" "0,0,0")] UNSPEC_INSN_FALSE_DEP)] - "TARGET_AVX512F && ( == 64 || TARGET_AVX512VL || TARGET_EVEX512)" + "TARGET_AVX512F" { if (TARGET_AVX512VL) return "vpternlog\t{$0x55, %1, %0, %0|%0, %0, %1, 0x55}"; @@ -18509,7 +18454,7 @@ (not: (match_operand: 1 "nonimmediate_operand"))))] " == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)" + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)" [(set (match_dup 0) (xor:VI48_AVX512F (vec_duplicate:VI48_AVX512F (match_dup 1)) @@ -18663,8 +18608,7 @@ (symbol_ref " == 64 || TARGET_AVX512VL") (eq_attr "alternative" "4") (symbol_ref " == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 - && !TARGET_PREFER_AVX256)") + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)") ] (const_string "*")))]) @@ -18708,7 +18652,7 @@ (match_operand: 1 "nonimmediate_operand"))) (match_operand:VI 2 "vector_operand")))] " == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)" + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)" [(set (match_dup 3) (vec_duplicate:VI (match_dup 1))) (set (match_dup 0) @@ -18723,7 +18667,7 @@ (match_operand: 1 "nonimmediate_operand"))) (match_operand:VI 2 "vector_operand")))] " == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)" + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)" [(set (match_dup 3) (vec_duplicate:VI (match_dup 1))) (set (match_dup 0) @@ -19017,7 +18961,7 @@ (match_operand:VI 1 "bcst_vector_operand" "0,m, 0,vBr")) (match_operand:VI 2 "bcst_vector_operand" "m,0,vBr, 0")))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && (register_operand (operands[1], mode) || register_operand (operands[2], mode))" { @@ -19050,7 +18994,7 @@ (match_operand:VI 1 "bcst_vector_operand" "%0, 0") (match_operand:VI 2 "bcst_vector_operand" " m,vBr"))))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && (register_operand (operands[1], mode) || register_operand (operands[2], mode))" { @@ -19081,7 +19025,7 @@ (not:VI (match_operand:VI 1 "bcst_vector_operand" "%0, 0")) (not:VI (match_operand:VI 2 "bcst_vector_operand" "m,vBr"))))] "( == 64 || TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)) + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)) && (register_operand (operands[1], mode) || register_operand (operands[2], mode))" { @@ -19103,7 +19047,7 @@ (const_string "*")))]) (define_mode_iterator AVX512ZEXTMASK - [(DI "TARGET_AVX512BW && TARGET_EVEX512") (SI "TARGET_AVX512BW") HI]) + [(DI "TARGET_AVX512BW") (SI "TARGET_AVX512BW") HI]) (define_insn "_testm3" [(set (match_operand: 0 "register_operand" "=k") @@ -19352,7 +19296,7 @@ (const_int 60) (const_int 61) (const_int 62) (const_int 63)])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpacksswb\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "") @@ -19421,7 +19365,7 @@ (const_int 14) (const_int 15) (const_int 28) (const_int 29) (const_int 30) (const_int 31)])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpackssdw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "") @@ -19483,7 +19427,7 @@ (const_int 61) (const_int 125) (const_int 62) (const_int 126) (const_int 63) (const_int 127)])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpunpckhbw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -19579,7 +19523,7 @@ (const_int 53) (const_int 117) (const_int 54) (const_int 118) (const_int 55) (const_int 119)])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpunpcklbw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -19803,7 +19747,7 @@ (const_int 11) (const_int 27) (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpunpckhdq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -19858,7 +19802,7 @@ (const_int 9) (const_int 25) (const_int 12) (const_int 28) (const_int 13) (const_int 29)])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpunpckldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -20564,7 +20508,7 @@ (match_operand:SI 2 "const_0_to_255_operand") (match_operand:V16SI 3 "register_operand") (match_operand:HI 4 "register_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { int mask = INTVAL (operands[2]); emit_insn (gen_avx512f_pshufd_1_mask (operands[0], operands[1], @@ -20608,7 +20552,7 @@ (match_operand 15 "const_12_to_15_operand") (match_operand 16 "const_12_to_15_operand") (match_operand 17 "const_12_to_15_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512 + "TARGET_AVX512F && INTVAL (operands[2]) + 4 == INTVAL (operands[6]) && INTVAL (operands[3]) + 4 == INTVAL (operands[7]) && INTVAL (operands[4]) + 4 == INTVAL (operands[8]) @@ -20774,7 +20718,7 @@ [(match_operand:V32HI 1 "nonimmediate_operand" "vm") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_PSHUFLW))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpshuflw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -20950,7 +20894,7 @@ [(match_operand:V32HI 1 "nonimmediate_operand" "vm") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_PSHUFHW))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpshufhw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -21484,7 +21428,7 @@ (match_operand:V4TI 1 "register_operand" "v") (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vextracti32x4\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "length_immediate" "1") @@ -21492,7 +21436,7 @@ (set_attr "mode" "XI")]) (define_mode_iterator VEXTRACTI128_MODE - [(V4TI "TARGET_AVX512F && TARGET_EVEX512") V2TI]) + [(V4TI "TARGET_AVX512F") V2TI]) (define_split [(set (match_operand:TI 0 "nonimmediate_operand") @@ -21515,7 +21459,7 @@ && VECTOR_MODE_P (GET_MODE (operands[1])) && ((TARGET_SSE && GET_MODE_SIZE (GET_MODE (operands[1])) == 16) || (TARGET_AVX && GET_MODE_SIZE (GET_MODE (operands[1])) == 32) - || (TARGET_AVX512F && TARGET_EVEX512 + || (TARGET_AVX512F && GET_MODE_SIZE (GET_MODE (operands[1])) == 64)) && (mode == SImode || TARGET_64BIT || MEM_P (operands[0]))" [(set (match_dup 0) (vec_select:SWI48x (match_dup 1) @@ -22890,7 +22834,7 @@ (const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix" "evex") @@ -23404,10 +23348,10 @@ ;; Mode iterator to handle singularity w/ absence of V2DI and V4DI ;; modes for abs instruction on pre AVX-512 targets. (define_mode_iterator VI1248_AVX512VL_AVX512BW - [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX2") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX2") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX512VL") + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX2") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) (define_insn "*abs2" @@ -24235,7 +24179,7 @@ [(set (match_operand:V32HI 0 "register_operand" "=v") (any_extend:V32HI (match_operand:V32QI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "vpmovbw\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -24249,7 +24193,7 @@ (match_operand:V64QI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:V32HI (match_dup 1)))] @@ -24269,7 +24213,7 @@ (match_operand:V64QI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" [(match_operand 5 "const_int_operand")])))] - "TARGET_AVX512BW && TARGET_EVEX512" + "TARGET_AVX512BW" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:V32HI (match_dup 1)))] @@ -24282,7 +24226,7 @@ [(set (match_operand:V32HI 0 "register_operand") (any_extend:V32HI (match_operand:V32QI 1 "nonimmediate_operand")))] - "TARGET_AVX512BW && TARGET_EVEX512") + "TARGET_AVX512BW") (define_insn "sse4_1_v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,Yw") @@ -24430,7 +24374,7 @@ [(set (match_operand:V16SI 0 "register_operand" "=v") (any_extend:V16SI (match_operand:V16QI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovbd\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -24440,7 +24384,7 @@ [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16QI 1 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_insn "avx2_v8qiv8si2" [(set (match_operand:V8SI 0 "register_operand" "=v") @@ -24573,7 +24517,7 @@ [(set (match_operand:V16SI 0 "register_operand" "=v") (any_extend:V16SI (match_operand:V16HI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovwd\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -24583,7 +24527,7 @@ [(set (match_operand:V16SI 0 "register_operand") (any_extend:V16SI (match_operand:V16HI 1 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_insn_and_split "avx512f_zero_extendv16hiv16si2_1" [(set (match_operand:V32HI 0 "register_operand" "=v") @@ -24593,7 +24537,7 @@ (match_operand:V32HI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:V16SI (match_dup 1)))] @@ -24817,7 +24761,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovbq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -24827,7 +24771,7 @@ [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8QI 1 "memory_operand" "m")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovbq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -24845,7 +24789,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX512F && TARGET_EVEX512 && ix86_pre_reload_split ()" + "TARGET_AVX512F && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -24856,7 +24800,7 @@ [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8QI 1 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { if (!MEM_P (operands[1])) { @@ -24998,7 +24942,7 @@ [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8HI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovwq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -25008,7 +24952,7 @@ [(set (match_operand:V8DI 0 "register_operand") (any_extend:V8DI (match_operand:V8HI 1 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_insn "avx2_v4hiv4di2" [(set (match_operand:V4DI 0 "register_operand" "=v") @@ -25135,7 +25079,7 @@ [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8SI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vpmovdq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -25149,7 +25093,7 @@ (match_operand:V16SI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:V8DI (match_dup 1)))] @@ -25168,7 +25112,7 @@ (match_operand:V16SI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" [(match_operand 5 "const_int_operand")])))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "#" "&& reload_completed" [(set (match_dup 0) (zero_extend:V8DI (match_dup 1)))] @@ -25180,7 +25124,7 @@ [(set (match_operand:V8DI 0 "register_operand" "=v") (any_extend:V8DI (match_operand:V8SI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_insn "avx2_v4siv4di2" [(set (match_operand:V4DI 0 "register_operand" "=v") @@ -25581,7 +25525,7 @@ [(match_operand:V16SI 0 "register_operand") (match_operand:V16SF 1 "nonimmediate_operand") (match_operand:SI 2 "const_0_to_15_operand")] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { rtx tmp = gen_reg_rtx (V16SFmode); emit_insn (gen_avx512f_rndscalev16sf (tmp, operands[1], operands[2])); @@ -26799,7 +26743,7 @@ (ashiftrt:V8DI (match_operand:V8DI 1 "register_operand") (match_operand:V8DI 2 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_expand "vashrv4di3" [(set (match_operand:V4DI 0 "register_operand") @@ -26890,7 +26834,7 @@ [(set (match_operand:V16SI 0 "register_operand") (ashiftrt:V16SI (match_operand:V16SI 1 "register_operand") (match_operand:V16SI 2 "nonimmediate_operand")))] - "TARGET_AVX512F && TARGET_EVEX512") + "TARGET_AVX512F") (define_expand "vashrv8si3" [(set (match_operand:V8SI 0 "register_operand") @@ -27333,12 +27277,12 @@ (set_attr "mode" "OI")]) (define_mode_attr pbroadcast_evex_isa - [(V64QI "avx512bw_512") (V32QI "avx512bw") (V16QI "avx512bw") - (V32HI "avx512bw_512") (V16HI "avx512bw") (V8HI "avx512bw") - (V16SI "avx512f_512") (V8SI "avx512f") (V4SI "avx512f") - (V8DI "avx512f_512") (V4DI "avx512f") (V2DI "avx512f") - (V32HF "avx512bw_512") (V16HF "avx512bw") (V8HF "avx512bw") - (V32BF "avx512bw_512") (V16BF "avx512bw") (V8BF "avx512bw")]) + [(V64QI "avx512bw") (V32QI "avx512bw") (V16QI "avx512bw") + (V32HI "avx512bw") (V16HI "avx512bw") (V8HI "avx512bw") + (V16SI "avx512f") (V8SI "avx512f") (V4SI "avx512f") + (V8DI "avx512f") (V4DI "avx512f") (V2DI "avx512f") + (V32HF "avx512bw") (V16HF "avx512bw") (V8HF "avx512bw") + (V32BF "avx512bw") (V16BF "avx512bw") (V8BF "avx512bw")]) (define_insn "avx2_pbroadcast" [(set (match_operand:VIHFBF 0 "register_operand" "=x,v") @@ -27882,7 +27826,7 @@ (set (attr "enabled") (if_then_else (eq_attr "alternative" "1") (symbol_ref "TARGET_AVX512F && !TARGET_AVX512VL - && TARGET_EVEX512 && !TARGET_PREFER_AVX256") + && !TARGET_PREFER_AVX256") (const_string "*")))]) (define_insn "*vec_dupv4si" @@ -27910,7 +27854,7 @@ (set (attr "enabled") (if_then_else (eq_attr "alternative" "1") (symbol_ref "TARGET_AVX512F && !TARGET_AVX512VL - && TARGET_EVEX512 && !TARGET_PREFER_AVX256") + && !TARGET_PREFER_AVX256") (const_string "*")))]) (define_insn "*vec_dupv2di" @@ -27941,8 +27885,7 @@ (if_then_else (eq_attr "alternative" "2") (symbol_ref "TARGET_AVX512VL - || (TARGET_AVX512F && TARGET_EVEX512 - && !TARGET_PREFER_AVX256)") + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)") (const_string "*")))]) (define_insn "avx2_vbroadcasti128_" @@ -28022,7 +27965,7 @@ [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "prefix" "maybe_evex") - (set_attr "isa" "avx2,noavx2,avx2,avx512f_512,noavx2") + (set_attr "isa" "avx2,noavx2,avx2,avx512f,noavx2") (set_attr "mode" ",V8SF,,,V8SF")]) (define_split @@ -28086,8 +28029,8 @@ ;; For broadcast[i|f]32x2. Yes there is no v4sf version, only v4si. (define_mode_iterator VI4F_BRCST32x2 - [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") - (V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V16SF (V8SF "TARGET_AVX512VL")]) (define_mode_attr 64x2mode [(V8DF "V2DF") (V8DI "V2DI") (V4DI "V2DI") (V4DF "V2DF")]) @@ -28137,8 +28080,7 @@ ;; For broadcast[i|f]64x2 (define_mode_iterator VI8F_BRCST64x2 - [(V8DI "TARGET_EVEX512") (V8DF "TARGET_EVEX512") - (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) + [V8DI V8DF (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")]) (define_insn "avx512dq_broadcast_1" [(set (match_operand:VI8F_BRCST64x2 0 "register_operand" "=v,v") @@ -28194,27 +28136,26 @@ (set_attr "mode" "")]) (define_mode_iterator VPERMI2 - [(V16SI "TARGET_EVEX512") (V16SF "TARGET_EVEX512") - (V8DI "TARGET_EVEX512") (V8DF "TARGET_EVEX512") + [V16SI V16SF V8DI V8DF (V8SI "TARGET_AVX512VL") (V8SF "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) (define_mode_iterator VPERMI2I - [(V16SI "TARGET_EVEX512") (V8DI "TARGET_EVEX512") + [V16SI V8DI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) @@ -28889,29 +28830,28 @@ ;; Modes handled by vec_init expanders. (define_mode_iterator VEC_INIT_MODE - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI - (V32HF "TARGET_AVX512F && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512F && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") - (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2") - (V4TI "TARGET_AVX512F && TARGET_EVEX512") (V2TI "TARGET_AVX")]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512F") (V16BF "TARGET_AVX") V8BF + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2") + (V4TI "TARGET_AVX512F") (V2TI "TARGET_AVX")]) ;; Likewise, but for initialization from half sized vectors. ;; Thus, these are all VEC_INIT_MODE modes except V2??. (define_mode_iterator VEC_INIT_HALF_MODE - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") - (V32HF "TARGET_AVX512F && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF - (V32BF "TARGET_AVX512F && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF - (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF - (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") - (V4TI "TARGET_AVX512F && TARGET_EVEX512")]) + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") + (V32HF "TARGET_AVX512F") (V16HF "TARGET_AVX") V8HF + (V32BF "TARGET_AVX512F") (V16BF "TARGET_AVX") V8BF + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") + (V4TI "TARGET_AVX512F")]) (define_expand "vec_init" [(match_operand:VEC_INIT_MODE 0 "register_operand") @@ -29172,7 +29112,7 @@ (unspec:V16SF [(match_operand:V16HI 1 "" "")] UNSPEC_VCVTPH2PS))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtph2ps\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -29262,7 +29202,7 @@ UNSPEC_VCVTPS2PH) (match_operand:V16HI 3 "nonimm_or_0_operand") (match_operand:HI 4 "register_operand")))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" { int round = INTVAL (operands[2]); /* Separate {sae} from rounding control imm, @@ -29281,7 +29221,7 @@ [(match_operand:V16SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -29293,7 +29233,7 @@ [(match_operand:V16SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] - "TARGET_AVX512F && TARGET_EVEX512" + "TARGET_AVX512F" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") @@ -30272,7 +30212,7 @@ (match_operand:V8DI 2 "register_operand" "v") (match_operand:V8DI 3 "nonimmediate_operand" "vm")] VPMADD52))] - "TARGET_AVX512IFMA && TARGET_EVEX512" + "TARGET_AVX512IFMA" "vpmadd52\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "evex") @@ -30643,7 +30583,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSD))] - "TARGET_AVX512VNNI && TARGET_EVEX512" + "TARGET_AVX512VNNI" "vpdpbusd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -30712,7 +30652,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSDS))] - "TARGET_AVX512VNNI && TARGET_EVEX512" + "TARGET_AVX512VNNI" "vpdpbusds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -30781,7 +30721,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSD))] - "TARGET_AVX512VNNI && TARGET_EVEX512" + "TARGET_AVX512VNNI" "vpdpwssd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -30850,7 +30790,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSDS))] - "TARGET_AVX512VNNI && TARGET_EVEX512" + "TARGET_AVX512VNNI" "vpdpwssds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -31006,8 +30946,7 @@ (set_attr "mode" "")]) (define_mode_iterator VI48_AVX512VP2VL - [(V8DI "TARGET_EVEX512") - (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + [V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) (define_mode_iterator MASK_DWI [P2QI P2HI]) @@ -31049,12 +30988,12 @@ (unspec:P2HI [(match_operand:V16SI 1 "register_operand" "v") (match_operand:V16SI 2 "vector_operand" "vm")] UNSPEC_VP2INTERSECT))] - "TARGET_AVX512VP2INTERSECT && TARGET_EVEX512" + "TARGET_AVX512VP2INTERSECT" "vp2intersectd\t{%2, %1, %0|%0, %1, %2}" [(set_attr ("prefix") ("evex"))]) (define_mode_iterator VF_AVX512BF16VL - [(V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + [V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) ;; Converting from BF to SF (define_mode_attr bf16_cvt_2sf [(V32BF "V16SF") (V16BF "V8SF") (V8BF "V4SF")]) @@ -31174,7 +31113,7 @@ "vcvtneps2bf16{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}") (define_mode_iterator VF1_AVX512_256 - [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) + [V16SF (V8SF "TARGET_AVX512VL")]) (define_expand "avx512f_cvtneps2bf16__maskz" [(match_operand: 0 "register_operand") @@ -31220,7 +31159,7 @@ [(set (match_operand:V16BF 0 "register_operand") (float_truncate:V16BF (match_operand:V16SF 1 "nonimmediate_operand")))] - "TARGET_AVX512BW && TARGET_EVEX512 + "TARGET_AVX512BW && !HONOR_NANS (BFmode) && !flag_rounding_math && (flag_unsafe_math_optimizations || TARGET_AVX512BF16)" { @@ -31504,10 +31443,10 @@ ;; vinserti64x4 $0x1, %ymm15, %zmm15, %zmm15 (define_mode_iterator INT_BROADCAST_MODE - [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI - (V32HI "TARGET_AVX512F && TARGET_EVEX512") (V16HI "TARGET_AVX") V8HI - (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI - (V8DI "TARGET_AVX512F && TARGET_EVEX512 && TARGET_64BIT") + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI + (V32HI "TARGET_AVX512F") (V16HI "TARGET_AVX") V8HI + (V16SI "TARGET_AVX512F") (V8SI "TARGET_AVX") V4SI + (V8DI "TARGET_AVX512F && TARGET_64BIT") (V4DI "TARGET_AVX && TARGET_64BIT") (V2DI "TARGET_64BIT")]) ;; Broadcast from an integer. NB: Enable broadcast only if we can move diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h index 15d8e964a32a..64f3c2082b70 100644 --- a/gcc/config/i386/vaesintrin.h +++ b/gcc/config/i386/vaesintrin.h @@ -66,9 +66,9 @@ _mm256_aesenclast_epi128 (__m256i __A, __m256i __B) #endif /* __DISABLE_VAES__ */ -#if !defined(__VAES__) || !defined(__AVX512F__) || !defined(__EVEX512__) +#if !defined(__VAES__) || !defined(__AVX512F__) #pragma GCC push_options -#pragma GCC target("vaes,avx512f,evex512") +#pragma GCC target("vaes,avx512f") #define __DISABLE_VAESF__ #endif /* __VAES__ */ diff --git a/gcc/config/i386/vpclmulqdqintrin.h b/gcc/config/i386/vpclmulqdqintrin.h index 2b36c37186bc..a02ab38fd5be 100644 --- a/gcc/config/i386/vpclmulqdqintrin.h +++ b/gcc/config/i386/vpclmulqdqintrin.h @@ -28,9 +28,9 @@ #ifndef _VPCLMULQDQINTRIN_H_INCLUDED #define _VPCLMULQDQINTRIN_H_INCLUDED -#if !defined(__VPCLMULQDQ__) || !defined(__AVX512F__) || !defined(__EVEX512__) +#if !defined(__VPCLMULQDQ__) || !defined(__AVX512F__) #pragma GCC push_options -#pragma GCC target("vpclmulqdq,avx512f,evex512") +#pragma GCC target("vpclmulqdq,avx512f") #define __DISABLE_VPCLMULQDQF__ #endif /* __VPCLMULQDQF__ */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 37dae2552d6a..442fce653a40 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6684,23 +6684,10 @@ Enable/disable the generation of the USER_MSR instructions. Enable/disable the generation of the APX features, including EGPR, PUSH2POP2, NDD and PPX. -@cindex @code{target("avx10.1-256")} function attribute, x86 -@item avx10.1-256 -@itemx no-avx10.1-256 -Enable the generation of the AVX10.1 instructions with 256 bit support. -Disable the generation of the AVX10.1 instructions. - @cindex @code{target("avx10.1")} function attribute, x86 @item avx10.1 @itemx no-avx10.1 -Enable the generation of the AVX10.1 instructions with 512 bit support. -Disable the generation of the AVX10.1 instructions. - -@cindex @code{target("avx10.1-512")} function attribute, x86 -@item avx10.1-512 -@itemx no-avx10.1-512 -Enable the generation of the AVX10.1 instructions with 512 bit support. -Disable the generation of the AVX10.1 instructions. +Enable/Disable the generation of the AVX10.1 instructions. @cindex @code{target("avx10.2")} function attribute, x86 @item avx10.2 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 83c63ce6ae53..52cfdb998715 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1496,8 +1496,8 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mamx-fp8 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 --mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs -mamx-movrs +-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs +-mamx-movrs -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -35742,12 +35742,6 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mavx10.1 @itemx -mavx10.1 @need 200 -@opindex mavx10.1-256 -@itemx -mavx10.1-256 -@need 200 -@opindex mavx10.1-512 -@itemx -mavx10.1-512 -@need 200 @opindex mavx10.2 @itemx -mavx10.2 @need 200 @@ -36536,11 +36530,6 @@ To invoke egpr usage in inline asm, use new compiler option -mapx-inline-asm-use-gpr32 and user should ensure the instruction supports EGPR. -@opindex mevex512 -@item -mevex512 -@itemx -mno-evex512 -Enables/disables 512-bit vector. It will be default on if AVX512F is enabled. - @end table These @samp{-m} switches are supported in addition to the above diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 1c718c414129..91fadc6ed01d 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2619,15 +2619,9 @@ Target supports compiling @code{avx} instructions. @item avx_runtime Target supports the execution of @code{avx} instructions. -@item avx10.1-256 -Target supports the execution of @code{avx10.1-256} instructions. - @item avx10.1 Target supports the execution of @code{avx10.1} instructions. -@item avx10.1-512 -Target supports the execution of @code{avx10.1-512} instructions. - @item avx10.2 Target supports the execution of @code{avx10.2} instructions. diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c index bd3249e6fc25..cfd9662bb139 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c @@ -1,6 +1,5 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c deleted file mode 100644 index dba2a4e0e2dd..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-10.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c deleted file mode 100644 index 608817a45ab2..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-11.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f" } */ -/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c deleted file mode 100644 index 1650f2682cb0..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */ -/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c deleted file mode 100644 index a864e96c2627..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f"))) __m512d -foo () -{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c deleted file mode 100644 index 76573e644fe5..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1-256"))) __m512d -foo () -{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c deleted file mode 100644 index b227cf3e0ec5..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-15.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f,no-evex512"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c deleted file mode 100644 index b3fdb3f3d4f5..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-16.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c deleted file mode 100644 index 09f125215dc2..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-avx10.1-512"))) __m512d -foo () -{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c deleted file mode 100644 index c1edce8fedee..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-18.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-avx512f"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c deleted file mode 100644 index 25b58872a1af..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx512f"))) __m512d -foo () -{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c index 19962bc2a37a..bf1de231a945 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-2.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ /* { dg-final { scan-assembler "%zmm" } } */ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c deleted file mode 100644 index a2230654114b..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-20.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mno-avx512f" } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1"))) __m512d -foo () -{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c deleted file mode 100644 index 2ae437e6ebf0..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c +++ /dev/null @@ -1,8 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */ -/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c deleted file mode 100644 index df7bffb1bdfc..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("evex512"))) __m512d -foo () -{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c deleted file mode 100644 index 1f8458480fe2..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not "%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("avx10.1-256"))) __m512d -foo () -{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c b/gcc/testsuite/gcc.target/i386/avx10_1-26.c deleted file mode 100644 index d8874042da96..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-26.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */ -/* { dg-require-ifunc "" } */ - -#include -__attribute__((target_clones ("default","avx10.1"))) -__m512d foo(__m512d a, __m512d b) -{ - return a + b; -} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c index 992364af6d80..3be988a1a62b 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c index b3d26032256d..fbc92d5c4cae 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-4.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ /* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ #include diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c new file mode 100644 index 000000000000..bada568ad94a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f -Wno-psabi" } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c new file mode 100644 index 000000000000..192d1d1ae9a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx512f -mno-avx10.1" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c index fb74ffba0870..d8874042da96 100644 --- a/gcc/testsuite/gcc.target/i386/avx10_1-7.c +++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c @@ -1,6 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ +/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */ +/* { dg-require-ifunc "" } */ -#include "avx10_1-2.c" +#include +__attribute__((target_clones ("default","avx10.1"))) +__m512d foo(__m512d a, __m512d b) +{ + return a + b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c deleted file mode 100644 index dbb7d6460320..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c +++ /dev/null @@ -1,6 +0,0 @@ -/* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -#include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c deleted file mode 100644 index b95173892a42..000000000000 --- a/gcc/testsuite/gcc.target/i386/avx10_1-9.c +++ /dev/null @@ -1,7 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */ -/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler "%zmm" } } */ - -#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c deleted file mode 100644 index 89eb52803d51..000000000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-1.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ -/* { dg-final { scan-assembler-not ".%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__m512d -foo () -{ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c deleted file mode 100644 index 34740ffa6798..000000000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-2.c +++ /dev/null @@ -1,14 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -#include - -long long -foo (long long c) -{ - register long long a __asm ("k7") = c; - long long b = foo (a); - asm volatile ("" : "+k" (b)); - return b; -} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-3.c b/gcc/testsuite/gcc.target/i386/noevex512-3.c deleted file mode 100644 index 10e00c2d61c2..000000000000 --- a/gcc/testsuite/gcc.target/i386/noevex512-3.c +++ /dev/null @@ -1,13 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=x86-64 -Wno-psabi -mavx512f" } */ -/* { dg-final { scan-assembler-not ".%zmm" } } */ - -typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); - -__attribute__ ((target ("no-evex512"))) __m512d -foo () -{ - __m512d a, b; - a = a + b; - return a; -} diff --git a/gcc/testsuite/gcc.target/i386/pr111068.c b/gcc/testsuite/gcc.target/i386/pr111068.c index 70c1e9a6b3b6..49a853daf303 100644 --- a/gcc/testsuite/gcc.target/i386/pr111068.c +++ b/gcc/testsuite/gcc.target/i386/pr111068.c @@ -1,7 +1,6 @@ /* PR target/111068 */ /* { dg-do compile } */ /* { dg-options "-ffloat-store -mavx10.1" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef _Float16 __attribute__((__vector_size__ (8))) V; V u, v, w; diff --git a/gcc/testsuite/gcc.target/i386/pr111889.c b/gcc/testsuite/gcc.target/i386/pr111889.c deleted file mode 100644 index 4f7682a28b7e..000000000000 --- a/gcc/testsuite/gcc.target/i386/pr111889.c +++ /dev/null @@ -1,10 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -march=x86-64" } */ - -#include - -__attribute__ ((target ("no-evex512,avx512vl"))) -__m256d foo (__m256d __W, __mmask8 __U, __m256d __A) -{ - return _mm256_mask_mov_pd (__W, __U, __A); -} diff --git a/gcc/testsuite/gcc.target/i386/pr111907.c b/gcc/testsuite/gcc.target/i386/pr111907.c deleted file mode 100644 index cadc9e456832..000000000000 --- a/gcc/testsuite/gcc.target/i386/pr111907.c +++ /dev/null @@ -1,9 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-mavx512f -mno-evex512" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ - -_Float128 -foo (_Float128 d, _Float128 e) -{ - return __builtin_copysignf128 (d, e); -} diff --git a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c index d34ebb7a6a09..d2753cbdc594 100644 --- a/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c +++ b/gcc/testsuite/gcc.target/i386/pr117240_avx512f.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -mvaes -mevex512 -mno-xsave -Wno-psabi" } */ -/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ +/* { dg-options "-O2 -mvaes -mno-xsave -Wno-psabi" } */ typedef __attribute__((__vector_size__(64))) char V; diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c index b46921cedaa2..c36b4ef1bce2 100644 --- a/gcc/testsuite/gcc.target/i386/pr117946.c +++ b/gcc/testsuite/gcc.target/i386/pr117946.c @@ -1,7 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-require-effective-target dfp } */ /* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */ -/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1 while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to all machines 512 bit vector size supported" "" { target *-*-* } 0 } */ typedef __attribute__((__vector_size__ (64))) _Decimal32 V; void