From: Bernd Edlinger <bernd.edlinger@hotmail.de>
Date: Mon, 6 Oct 2025 06:37:20 +0000 (+0200)
Subject: Improve the CPUINFO display for RISC-V
X-Git-Tag: 4.0-PRE-CLANG-FORMAT-WEBKIT~226
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c05ea2fdb7f7687c2df1b611ece37be1bd03b011;p=thirdparty%2Fopenssl.git

Improve the CPUINFO display for RISC-V

Prefix the base architecture to the displayed RISC-V
architecture string, so the displayed OPENSSL_riscvcap
environment value can be used as is, since otherwise
the OPENSSL_cpuid_setup would ignore the first extension,
as it is expected to be the base architecture, usually
"RV64GC" or similar.
See the comment at parse_env in crypto/riscvcap.c
Furthermore also print the VLEN value, if the V-extension
is given, since that makes a significant difference
which assembler modules are activated by the V-extension.

Reviewed-by: Paul Dale <paul.dale@oracle.com>
Reviewed-by: Dmitry Belyavskiy <beldmit@gmail.com>
(Merged from https://github.com/openssl/openssl/pull/28760)
---

diff --git a/crypto/info.c b/crypto/info.c
index de69a575337..7a256a7de64 100644
--- a/crypto/info.c
+++ b/crypto/info.c
@@ -127,27 +127,54 @@ DEFINE_RUN_ONCE_STATIC(init_info_strings)
                      " env:%s", env);
 # elif defined(__riscv)
     const char *env;
-    char sep = '=';
+    size_t i;
 
     BIO_snprintf(ossl_cpu_info_str, sizeof(ossl_cpu_info_str),
-                 CPUINFO_PREFIX "OPENSSL_riscvcap");
-    for (size_t i = 0; i < kRISCVNumCaps; ++i) {
+                 CPUINFO_PREFIX "OPENSSL_riscvcap=RV"
+#  if __riscv_xlen == 32
+                 "32"
+#  elif __riscv_xlen == 64
+                 "64"
+#  elif __riscv_xlen == 128
+                 "128"
+#  endif
+#  if defined(__riscv_i) && defined(__riscv_m) && defined(__riscv_a) \
+      && defined(__riscv_f) && defined(__riscv_d) \
+      && defined(__riscv_zicsr) && defined(__riscv_zifencei)
+                 "G" /* shorthand for IMAFD_Zicsr_Zifencei */
+#  else
+#   ifdef __riscv_i
+                 "I"
+#   endif
+#   ifdef __riscv_m
+                 "M"
+#   endif
+#   ifdef __riscv_a
+                 "A"
+#   endif
+#   ifdef __riscv_f
+                 "F"
+#   endif
+#   ifdef __riscv_d
+                 "D"
+#   endif
+#  endif
+#  ifdef __riscv_c
+                 "C"
+#  endif
+                 );
+    for (i = 0; i < kRISCVNumCaps; i++) {
         if (OPENSSL_riscvcap_P[RISCV_capabilities[i].index]
-                & (1 << RISCV_capabilities[i].bit_offset)) {
+                & (1 << RISCV_capabilities[i].bit_offset))
             /* Match, display the name */
             BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str),
                          sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str),
-                         "%c%s", sep, RISCV_capabilities[i].name);
-            /* Only the first sep is '=' */
-            sep = '_';
-        }
+                         "_%s", RISCV_capabilities[i].name);
     }
-    /* If no capability is found, add back the = */
-    if (sep == '=') {
+    if (RISCV_HAS_V())
         BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str),
                      sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str),
-                     "%c", sep);
-    }
+                     " vlen:%lu", riscv_vlen());
     if ((env = getenv("OPENSSL_riscvcap")) != NULL)
         BIO_snprintf(ossl_cpu_info_str + strlen(ossl_cpu_info_str),
                      sizeof(ossl_cpu_info_str) - strlen(ossl_cpu_info_str),
diff --git a/doc/man3/OPENSSL_riscvcap.pod b/doc/man3/OPENSSL_riscvcap.pod
index 1ebf20826a7..3113b98f336 100644
--- a/doc/man3/OPENSSL_riscvcap.pod
+++ b/doc/man3/OPENSSL_riscvcap.pod
@@ -189,15 +189,21 @@ Not available.
 Check currently detected capabilities
 
  $ openssl info -cpusettings
- OPENSSL_riscvcap=ZBA_ZBB_ZBC_ZBS_V
+ OPENSSL_riscvcap=RV64GC_ZBA_ZBB_ZBC_ZBS_V vlen:256
+
+Note: The first word in the displayed capabilities is the RISC-V base
+architecture value, which is derived from the compiler configuration.
+It is therefore not overridable by the environment variable.
+When the V extension is given the riscv_vlen value is always displayed,
+there is no way to override the riscv_vlen by the environment variable.
 
 Disables all instruction set extensions:
 
- OPENSSL_riscvcap="rv64gc"
+ export OPENSSL_riscvcap="rv64gc"
 
 Only enable the vector extension:
 
- OPENSSL_riscvcap="rv64gc_v"
+ export OPENSSL_riscvcap="rv64gc_v"
 
 =head1 COPYRIGHT