From: Andrey Belevantsev Date: Mon, 1 Apr 2013 08:34:20 +0000 (+0400) Subject: backport: re PR middle-end/45472 ([Middle-end volatile semantics] ICE: in move_op_asc... X-Git-Tag: releases/gcc-4.6.4~81 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c19cb871b533620264baf0723a2df1bbd7f91351;p=thirdparty%2Fgcc.git backport: re PR middle-end/45472 ([Middle-end volatile semantics] ICE: in move_op_ascend, at sel-sched.c:6124 with -fselective-scheduling2) Backport from mainline 2013-02-27 Andrey Belevantsev PR middle-end/45472 * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr when the may_trap_p bit of the exprs being merged differs. Reorder tests for speculativeness in the logical and operator. Backport from mainline 2013-03-05 Jakub Jelinek PR middle-end/56461 * sel-sched-ir.c (free_sched_pools): Release succs_info_pool.stack[succs_info_pool.max_top] vectors too if succs_info_pool.max_top isn't -1. Backport from mainline 2013-02-27 Andrey Belevantsev PR middle-end/45472 * gcc.dg/pr45472.c: New test. From-SVN: r197302 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e6f20740f64c..9015461bfaf2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +2013-04-01 Andrey Belevantsev + + Backport from mainline + 2013-02-27 Andrey Belevantsev + + PR middle-end/45472 + + * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr + when the may_trap_p bit of the exprs being merged differs. + Reorder tests for speculativeness in the logical and operator. + + Backport from mainline + 2013-03-05 Jakub Jelinek + + PR middle-end/56461 + * sel-sched-ir.c (free_sched_pools): Release + succs_info_pool.stack[succs_info_pool.max_top] vectors too + if succs_info_pool.max_top isn't -1. + 2013-04-01 Andrey Belevantsev Backport from mainline diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index 41440d894258..38c817eca370 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -1857,8 +1857,12 @@ merge_expr (expr_t to, expr_t from, insn_t split_point) /* Make sure that speculative pattern is propagated into exprs that have non-speculative one. This will provide us with consistent speculative bits and speculative patterns inside expr. */ - if (EXPR_SPEC_DONE_DS (to) == 0 - && EXPR_SPEC_DONE_DS (from) != 0) + if ((EXPR_SPEC_DONE_DS (from) != 0 + && EXPR_SPEC_DONE_DS (to) == 0) + /* Do likewise for volatile insns, so that we always retain + the may_trap_p bit on the resulting expression. */ + || (VINSN_MAY_TRAP_P (EXPR_VINSN (from)) + && !VINSN_MAY_TRAP_P (EXPR_VINSN (to)))) change_vinsn_in_expr (to, EXPR_VINSN (from)); merge_expr_data (to, from, split_point); @@ -4876,7 +4880,7 @@ free_sched_pools (void) free_alloc_pool (sched_lists_pool); gcc_assert (succs_info_pool.top == -1); - for (i = 0; i < succs_info_pool.max_top; i++) + for (i = 0; i <= succs_info_pool.max_top; i++) { VEC_free (rtx, heap, succs_info_pool.stack[i].succs_ok); VEC_free (rtx, heap, succs_info_pool.stack[i].succs_other); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b502eac159bd..5511389c779c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2013-04-01 Andrey Belevantsev + + Backport from mainline + 2013-02-27 Andrey Belevantsev + + PR middle-end/45472 + * gcc.dg/pr45472.c: New test. + 2013-03-22 H.J. Lu PR target/56560 diff --git a/gcc/testsuite/gcc.dg/pr45472.c b/gcc/testsuite/gcc.dg/pr45472.c new file mode 100644 index 000000000000..46a6373e519c --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr45472.c @@ -0,0 +1,84 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +} +/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */ +/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */ + +struct S +{ + volatile long vl; + int i; +}; +struct S s1, s2; + +void +foo (int j, int c) +{ + int i; + for (i = 0; i <= j; i++) + { + if (c) + s2.vl += s1.vl; + s1 = s2; + } +}