From: Sarthak Garg Date: Mon, 8 Sep 2025 10:41:22 +0000 (+0530) Subject: arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default X-Git-Tag: v6.19-rc1~100^2~14^2~29 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c3398456f6f6121e79f6c3d9bff00076cf7a3521;p=thirdparty%2Flinux.git arm64: dts: qcom: sm8550: Limit max SD HS mode frequency by default Due to an implementation detail in this SoC, additional passive electrical components are required to achieve the maximum rated speed of the SD controller when paired with a High-Speed SD Card. Without them, the clock frequency must be limited to 37.5 MHz for link stability. Because the reference design does not contain these components, most (derivative) boards do not have them either. To accommodate for that, apply the frequency limit by default and delegate lifting it to the odd boards that do contain the necessary onboard hardware. Signed-off-by: Sarthak Garg Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250908104122.2062653-5-quic_sartgarg@quicinc.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index aa3167d10a412..04e6db8f10305 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3224,6 +3224,7 @@ &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; bus-width = <4>; + max-sd-hs-hz = <37500000>; dma-coherent; /* Forbid SDR104/SDR50 - broken hw! */