From: Balaji Selvanathan Date: Fri, 13 Feb 2026 09:01:19 +0000 (+0530) Subject: clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support X-Git-Tag: v2026.04~8^2~5 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c4169dfa1dcc2dc4876b10e1b1dc3de6b96ffd80;p=thirdparty%2Fu-boot.git clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615 clock driver. This clock is required for proper PHY operation and eliminates clock-related warnings during USB initialization. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com Signed-off-by: Casey Connolly --- diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 65b8db04020..2087fc38f63 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -67,6 +67,7 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), + GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),