From: Richard Sandiford <richard.sandiford@linaro.org>
Date: Thu, 9 Nov 2017 15:19:15 +0000 (+0000)
Subject: Add a vect_masked_store target selector
X-Git-Tag: basepoints/gcc-9~3491
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c48a8e71c8b5d3e6bdffaec85b1e3b111814cee0;p=thirdparty%2Fgcc.git

Add a vect_masked_store target selector

This patch adds a target selector that says whether the target
supports IFN_MASK_STORE.

2017-11-09  Richard Sandiford  <richard.sandiford@linaro.org>
	    Alan Hayward  <alan.hayward@arm.com>
	    David Sherwood  <david.sherwood@arm.com>

gcc/
	* doc/sourcebuild.texi (vect_masked_store): Document.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_vect_masked_store):
	New proc.
	* gcc.dg/vect/vect-cselim-1.c (foo): Mention that the second loop
	is vectorizable with masked stores.  Update scan-tree-dump-times
	accordingly.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>

From-SVN: r254597
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 84e788f735ca..944a3a3bd7ab 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2017-11-09  Richard Sandiford  <richard.sandiford@linaro.org>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* doc/sourcebuild.texi (vect_masked_store): Document.
+
 2017-11-09  Richard Sandiford  <richard.sandiford@linaro.org>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index d200f7135bea..d5a90e518d67 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1403,6 +1403,9 @@ Target supports hardware vectors of @code{long}.
 @item vect_long_long
 Target supports hardware vectors of @code{long long}.
 
+@item vect_masked_store
+Target supports vector masked stores.
+
 @item vect_aligned_arrays
 Target aligns arrays to vector alignment boundary.
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8d7ad64cdca7..3ace82cb5f1f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2017-11-09  Richard Sandiford  <richard.sandiford@linaro.org>
+	    Alan Hayward  <alan.hayward@arm.com>
+	    David Sherwood  <david.sherwood@arm.com>
+
+	* lib/target-supports.exp (check_effective_target_vect_masked_store):
+	New proc.
+	* gcc.dg/vect/vect-cselim-1.c (foo): Mention that the second loop
+	is vectorizable with masked stores.  Update scan-tree-dump-times
+	accordingly.
+
 2017-11-09  Richard Sandiford  <richard.sandiford@linaro.org>
 	    Alan Hayward  <alan.hayward@arm.com>
 	    David Sherwood  <david.sherwood@arm.com>
diff --git a/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c b/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c
index 2b0101329840..e6ad865303c4 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-cselim-1.c
@@ -38,7 +38,7 @@ foo ()
         }
     }
 
-  /* Not vectorizable.  */
+  /* Only vectorizable with masked stores.  */
   for (i = 0; i < N; i++)
     {
       c = in1[i].b;
@@ -82,4 +82,5 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect"  { xfail { { vect_no_align && { ! vect_hw_misalign } } || { ! vect_strided2 } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect_masked_store } xfail { { vect_no_align && { ! vect_hw_misalign } } || { ! vect_strided2 } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target { vect_masked_store } } } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 9ef40198d1bb..54e203681bab 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -6433,6 +6433,12 @@ proc check_effective_target_vect_load_lanes { } {
     return $et_vect_load_lanes
 }
 
+# Return 1 if the target supports vector masked stores.
+
+proc check_effective_target_vect_masked_store { } {
+    return 0
+}
+
 # Return 1 if the target supports vector conditional operations, 0 otherwise.
 
 proc check_effective_target_vect_condition { } {