From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Sun, 23 Apr 2023 11:33:54 +0000 (+0800)
Subject: RISC-V: Add function comment for cleanup_insns.
X-Git-Tag: basepoints/gcc-15~9955
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c5a1fa59ae3f44059a79086cbc506800d4149b69;p=thirdparty%2Fgcc.git

RISC-V: Add function comment for cleanup_insns.

Add more comment for cleanup_insns.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function
	comment for cleanup_insns.
---

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index ac99028df431..fa68b8a04625 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3998,6 +3998,21 @@ pass_vsetvl::pre_vsetvl (void)
     commit_edge_insertions ();
 }
 
+/* Before VSETVL PASS, RVV instructions pattern is depending on AVL operand
+   implicitly. Since we will emit VSETVL instruction and make RVV instructions
+   depending on VL/VTYPE global status registers, we remove the such AVL operand
+   in the RVV instructions pattern here in order to remove AVL dependencies when
+   AVL operand is a register operand.
+
+   Before the VSETVL PASS:
+     li a5,32
+     ...
+     vadd.vv (..., a5)
+   After the VSETVL PASS:
+     li a5,32
+     vsetvli zero, a5, ...
+     ...
+     vadd.vv (..., const_int 0).  */
 void
 pass_vsetvl::cleanup_insns (void) const
 {