From: Junhui Liu Date: Tue, 19 May 2026 12:58:28 +0000 (+0800) Subject: net: dwc_eth_qos: add support for sun55i platform X-Git-Tag: v2026.10-rc1~1^2~1 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c5d3fac4becf7ca5db58a6937ddaf69df0070834;p=thirdparty%2Fu-boot.git net: dwc_eth_qos: add support for sun55i platform The Allwinner sun55i (A523/A527/T527) platform features the Synopsys DesignWare Ethernet QOS IP. To enable this GMAC controller in U-Boot, this introduces the glue layer responsible for configuring the corresponding clocks, resets, and syscon registers. This implementation is directly ported from upstream Linux kernel commit f603808a98af ("net: stmmac: Add support for Allwinner A523 GMAC200"). Link: https://patch.msgid.link/20250925191600.3306595-3-wens@kernel.org Signed-off-by: Junhui Liu --- diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4399c6c7a99..faa08e9ebba 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -284,6 +284,15 @@ config DWC_ETH_QOS_STM32 The Synopsys Designware Ethernet QOS IP block with the specific configuration used in STM32MP soc. +config DWC_ETH_QOS_SUNXI + bool "Synopsys DWC Ethernet QOS device support for Allwinner SoCs" + depends on DWC_ETH_QOS && ARCH_SUNXI + select REGMAP + select SUNXI_SYSCON + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in Allwinner SoCs. + config DWC_ETH_QOS_TEGRA186 bool "Synopsys DWC Ethernet QOS device support for TEGRA186" depends on DWC_ETH_QOS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 761f7f0f451..4c1f4094ab2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o +obj-$(CONFIG_DWC_ETH_QOS_SUNXI) += dwc_eth_qos_sunxi.o obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index b7e6299c307..e7cf68d011c 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1664,6 +1664,12 @@ static const struct udevice_id eqos_ids[] = { .compatible = "mediatek,mt8189-gmac", .data = (ulong)&eqos_mtk_config }, +#endif +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_SUNXI) + { + .compatible = "allwinner,sun55i-a523-gmac200", + .data = (ulong)&eqos_sunxi_config + }, #endif { } }; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 978b848b46e..ccb3c3a1453 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -318,3 +318,4 @@ extern struct eqos_config eqos_stm32mp25_config; extern struct eqos_config eqos_jh7110_config; extern struct eqos_config eqos_adi_config; extern struct eqos_config eqos_mtk_config; +extern struct eqos_config eqos_sunxi_config; diff --git a/drivers/net/dwc_eth_qos_sunxi.c b/drivers/net/dwc_eth_qos_sunxi.c new file mode 100644 index 00000000000..91d871dd271 --- /dev/null +++ b/drivers/net/dwc_eth_qos_sunxi.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Corentin Labbe + * Copyright (C) 2025 Chen-Yu Tsai + * Copyright (C) 2026 Junhui Liu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_eth_qos.h" + +#define SYSCON_REG 0x34 + +#define SYSCON_PHY_SELECT BIT(15) /* 1: internal, 0: external */ +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +struct sunxi_platform_data { + struct clk_bulk clks; + struct reset_ctl_bulk resets; +}; + +static int sunxi_gmac_set_syscon(struct udevice *dev, + phy_interface_t interface_type) +{ + struct regmap *regmap; + u32 val, reg = 0; + int ret; + + regmap = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(regmap)) { + dev_err(dev, "Unable to map syscon\n"); + return PTR_ERR(regmap); + } + + if (!dev_read_u32(dev, "tx-internal-delay-ps", &val)) { + if (val % 100) { + dev_err(dev, "tx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /= 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + + if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) { + dev_err(dev, "TX clock delay exceeds maximum\n"); + return -EINVAL; + } + + reg |= FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!dev_read_u32(dev, "rx-internal-delay-ps", &val)) { + if (val % 100) { + dev_err(dev, "rx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /= 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) { + dev_err(dev, "Invalid RX clock delay: %d\n", val); + return -EINVAL; + } + + reg |= FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (interface_type) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |= SYSCON_RMII_EN; + break; + default: + dev_err(dev, "Unsupported interface mode: %s\n", + phy_interface_strings[interface_type]); + return -EINVAL; + } + + ret = regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) { + dev_err(dev, "Failed to write to syscon\n"); + return ret; + } + + return 0; +} + +static int eqos_start_clks_sunxi(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data = pdata->priv_pdata; + + return clk_enable_bulk(&data->clks); +} + +static int eqos_stop_clks_sunxi(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data = pdata->priv_pdata; + + return clk_disable_bulk(&data->clks); +} + +static int eqos_start_resets_sunxi(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data = pdata->priv_pdata; + int ret; + + ret = reset_deassert_bulk(&data->resets); + if (ret) + return ret; + + return sunxi_gmac_set_syscon(dev, pdata->phy_interface); +} + +static int eqos_stop_resets_sunxi(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data = pdata->priv_pdata; + + return reset_assert_bulk(&data->resets); +} + +static int eqos_probe_resources_sunxi(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data; + struct udevice *phy_supply = NULL; + int ret; + + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "Failed to get base address: %d\n", ret); + return ret; + } + + data = calloc(1, sizeof(struct sunxi_platform_data)); + if (!data) + return -ENOMEM; + + pdata->priv_pdata = data; + + pdata->phy_interface = eqos->config->interface(dev); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Failed to get PHY interface mode\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); + if (ret) { + dev_err(dev, "Failed to get stmmaceth clock: %d\n", ret); + return ret; + } + + ret = reset_get_bulk(dev, &data->resets); + if (ret) { + dev_err(dev, "Failed to get resets: %d\n", ret); + return ret; + } + + ret = clk_get_bulk(dev, &data->clks); + if (ret) { + dev_err(dev, "Failed to get clocks: %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "phy-supply", &phy_supply); + if (ret && ret != -ENOENT) { + dev_err(dev, "Failed to get PHY supply: %d\n", ret); + return ret; + } + + if (phy_supply) { + ret = regulator_set_enable_if_allowed(phy_supply, true); + if (ret) { + dev_err(dev, "Failed to enable phy supply: %d\n", ret); + return ret; + } + } + } + + return 0; +} + +static int eqos_remove_resources_sunxi(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct sunxi_platform_data *data = pdata->priv_pdata; + + reset_assert_bulk(&data->resets); + clk_disable_bulk(&data->clks); + + return 0; +} + +static struct eqos_ops eqos_sunxi_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_sunxi, + .eqos_remove_resources = eqos_remove_resources_sunxi, + .eqos_stop_resets = eqos_stop_resets_sunxi, + .eqos_start_resets = eqos_start_resets_sunxi, + .eqos_stop_clks = eqos_stop_clks_sunxi, + .eqos_start_clks = eqos_start_clks_sunxi, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_null_ops, + .eqos_get_enetaddr = eqos_null_ops, +}; + +struct eqos_config __maybe_unused eqos_sunxi_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_150_250, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_sunxi_ops +};