From: John David Anglin <dave@hiauly1.hia.nrc.ca>
Date: Thu, 11 Jul 2002 18:22:02 +0000 (+0000)
Subject: pa.md (adddi3): Change predicate of operand 2 to adddi3_operand.
X-Git-Tag: releases/gcc-3.1.1~37
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c5d66b7d085da14ee78b5fd5ca1efe69d4e61b73;p=thirdparty%2Fgcc.git

pa.md (adddi3): Change predicate of operand 2 to adddi3_operand.

	* pa.md (adddi3): Change predicate of operand 2 to adddi3_operand.
	Remove comment.  Change predicate of 32-bit adddi3 insn pattern to
	arith11_operand.
	* pa-protos.h (adddi3_operand): Add prototype.
	* pa.c (cint_ok_for_move): Fix comment.
	(adddi3_operand): New function.
	(emit_move_sequence):  Don't directly split DImode constants on
	32-bit targets.

From-SVN: r55399
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8309c8229aa4..648b8bd2afb3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2002-07-11  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* pa.md (adddi3): Change predicate of operand 2 to adddi3_operand.
+	Remove comment.  Change predicate of 32-bit adddi3 insn pattern to
+	arith11_operand.
+	* pa-protos.h (adddi3_operand): Add prototype.
+	* pa.c (cint_ok_for_move): Fix comment.
+	(adddi3_operand): New function.
+	(emit_move_sequence):  Don't directly split DImode constants on
+	32-bit targets.
+
 2002-07-05  Stephane Carrez  <stcarrez@nerim.fr>
 
 	* config/m68hc11/m68hc11.md ("*movqi_68hc12"): Avoid allocating
diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h
index 0c81ae068148..163cf28528fe 100644
--- a/gcc/config/pa/pa-protos.h
+++ b/gcc/config/pa/pa-protos.h
@@ -63,6 +63,7 @@ extern rtx legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx));
 extern struct rtx_def *gen_cmp_fp PARAMS ((enum rtx_code, rtx, rtx));
 extern void hppa_encode_label PARAMS ((rtx));
 extern int arith11_operand PARAMS ((rtx, enum machine_mode));
+extern int adddi3_operand PARAMS ((rtx, enum machine_mode));
 extern int symbolic_expression_p PARAMS ((rtx));
 extern int hppa_address_cost PARAMS ((rtx));
 extern int symbolic_memory_operand PARAMS ((rtx, enum machine_mode));
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 3d98898a2a8f..c543c950c4ae 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -393,7 +393,7 @@ reg_before_reload_operand (op, mode)
   return 0;
 }
 
-/* Accept any constant that can be moved in one instructions into a
+/* Accept any constant that can be moved in one instruction into a
    general register.  */
 int
 cint_ok_for_move (intval)
@@ -529,6 +529,18 @@ arith11_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
 }
 
+/* Return truth value of whether OP can be used as an operand in a
+   adddi3 insn.  */
+int
+adddi3_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  || (GET_CODE (op) == CONST_INT
+	      && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
+}
+
 /* A constant integer suitable for use in a PRE_MODIFY memory
    reference.  */
 int
@@ -1695,9 +1707,13 @@ emit_move_sequence (operands, mode, scratch_reg)
 	  else
 	    temp = gen_reg_rtx (mode);
 
-	  if (GET_CODE (operand1) == CONST_INT)
+	  /* We don't directly split DImode constants on 32-bit targets
+	     because PLUS uses an 11-bit immediate and the insn sequence
+	     generated is not as efficient as the one using HIGH/LO_SUM.  */
+	  if (GET_CODE (operand1) == CONST_INT
+	      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
 	    {
-	      /* Directly break constant into low and high parts.  This
+	      /* Directly break constant into high and low parts.  This
 		 provides better optimization opportunities because various
 		 passes recognize constants split with PLUS but not LO_SUM.
 		 We use a 14-bit signed low part except when the addition
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index aa0c305d18f4..a0e3d80e7eb9 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3653,22 +3653,14 @@
 (define_expand "adddi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
-		 (match_operand:DI 2 "arith_operand" "")))]
+		 (match_operand:DI 2 "adddi3_operand" "")))]
   ""
   "")
 
-;; We allow arith_operand for operands2, even though strictly speaking it
-;; we would prefer to us arith11_operand since that's what the hardware
-;; can actually support.
-;;
-;; But the price of the extra reload in that case is worth the simplicity
-;; we get by allowing a trivial adddi3 expander to be used for both
-;; PA64 and PA32.
-
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (match_operand:DI 1 "register_operand" "%r")
-		 (match_operand:DI 2 "arith_operand" "rI")))]
+		 (match_operand:DI 2 "arith11_operand" "rI")))]
   "!TARGET_64BIT"
   "*
 {