From: Jerome Brunet Date: Wed, 14 Jan 2026 17:08:49 +0000 (+0100) Subject: arm64: dts: amlogic: a1: align the mmc clock setup X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c6ccd0d9a253b59125e5c625139799b41f0de3e0;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: amlogic: a1: align the mmc clock setup The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. A1 is particular in the way that is already has the mmc clock set to 24MHz by forcing the mux to select the board crystal. It works too, it is just slightly less readable. Align with what is being done with the other Amlogic platforms. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-2-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 27b68ed85c4c2..348411411f3d1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -674,11 +674,12 @@ clock-names = "core", "clkin0", "clkin1"; - assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; - assigned-clock-parents = <&xtal>; resets = <&reset RESET_SD_EMMC_A>; power-domains = <&pwrc PWRC_SD_EMMC_ID>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC>; + assigned-clock-rates = <24000000>; }; };