From: Han Gao <gaohan@iscas.ac.cn>
Date: Tue, 31 Mar 2026 17:12:47 +0000 (+0800)
Subject: dt-bindings: PCI: sophgo: Add dma-coherent property for SG2042
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c6d51515ee0b79a52b7e532b6b20067fa0cec96f;p=thirdparty%2Flinux.git

dt-bindings: PCI: sophgo: Add dma-coherent property for SG2042

Add dma-coherent as an allowed property in the SG2042 PCIe host controller
binding. SG2042's PCIe Root Complexes are cache-coherent with the CPU.

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260331171248.973014-2-gaohan@iscas.ac.cn
---

diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
index f8b7ca57fff14..ab482488b0475 100644
--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -30,6 +30,8 @@ properties:
   device-id:
     const: 0x2042
 
+  dma-coherent: true
+
   msi-parent: true
 
 allOf:
@@ -60,5 +62,6 @@ examples:
       vendor-id = <0x1f1c>;
       device-id = <0x2042>;
       cdns,no-bar-match-nbits = <48>;
+      dma-coherent;
       msi-parent = <&msi>;
     };