From: Pan Li Date: Wed, 16 Aug 2023 05:15:04 +0000 (+0800) Subject: RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API X-Git-Tag: basepoints/gcc-15~6906 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c6f65ce9483131b1996cbddf8aaaebe0d8e5141c;p=thirdparty%2Fgcc.git RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API This patch would like to support the rounding mode API for the VFCVT.X.F.V as the below samples. * __riscv_vfcvt_x_f_v_i32m1_rm * __riscv_vfcvt_x_f_v_i32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (enum frm_op_type): New type for frm. (BASE): New declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfcvt_x_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test. --- diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index f2124080ef9c..817d2ed016aa 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -58,6 +58,12 @@ enum lst_type LST_INDEXED, }; +enum frm_op_type +{ + NO_FRM, + HAS_FRM, +}; + /* Helper function to fold vleff and vlsegff. */ static gimple * fold_fault_load (gimple_folder &f) @@ -1662,10 +1668,15 @@ public: }; /* Implements vfcvt.x. */ -template +template class vfcvt_x : public function_base { public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + rtx expand (function_expander &e) const override { return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0))); @@ -2465,6 +2476,7 @@ static CONSTEXPR const vfclass vfclass_obj; static CONSTEXPR const vmerge vfmerge_obj; static CONSTEXPR const vmv_v vfmv_v_obj; static CONSTEXPR const vfcvt_x vfcvt_x_obj; +static CONSTEXPR const vfcvt_x vfcvt_x_frm_obj; static CONSTEXPR const vfcvt_x vfcvt_xu_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj; @@ -2714,6 +2726,7 @@ BASE (vfclass) BASE (vfmerge) BASE (vfmv_v) BASE (vfcvt_x) +BASE (vfcvt_x_frm) BASE (vfcvt_xu) BASE (vfcvt_rtz_x) BASE (vfcvt_rtz_xu) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 2a9381eec5e4..50a7d7ffb6f6 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -205,6 +205,7 @@ extern const function_base *const vfclass; extern const function_base *const vfmerge; extern const function_base *const vfmv_v; extern const function_base *const vfcvt_x; +extern const function_base *const vfcvt_x_frm; extern const function_base *const vfcvt_xu; extern const function_base *const vfcvt_rtz_x; extern const function_base *const vfcvt_rtz_xu; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 34def6bb82f1..8b6a7cc49f36 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -445,6 +445,8 @@ DEF_RVV_FUNCTION (vfcvt_rtz_xu, alu, full_preds, f_to_u_f_v_ops) DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops) DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops) +DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops) + // 13.18. Widening Floating-Point/Integer Type-Convert Instructions DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops) DEF_RVV_FUNCTION (vfwcvt_xu, alu, full_preds, f_to_wu_f_v_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c new file mode 100644 index 000000000000..e090f0f97e9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vint32m1_t +test_riscv_vfcvt_x_f_vv_i32m1_rm (vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1_rm (op1, 0, vl); +} + +vint32m1_t +test_vfcvt_x_f_vv_i32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1_rm_m (mask, op1, 1, vl); +} + +vint32m1_t +test_riscv_vfcvt_x_f_vv_i32m1 (vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1 (op1, vl); +} + +vint32m1_t +test_vfcvt_x_f_vv_i32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) { + return __riscv_vfcvt_x_f_v_i32m1_m (mask, op1, vl); +} + +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */