From: Siarhei Volkau <lis8215@gmail.com>
Date: Thu, 22 May 2025 14:52:17 +0000 (-0600)
Subject: [PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c77085970ec98916e12e079a5a9d9530b86aae71;p=thirdparty%2Fgcc.git

[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

Patch is originally from Siarhei Volkau <lis8215@gmail.com>.

RISC-V has a zero register (x0) which we can use to store zero into memory
without loading the constant into a distinct register. Adjust the constraints
of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into
memory using x0 as the source register.

This patch only affects RISC-V. It has been regression tested on riscv64-elf.
Jeff has also tested this in his tester (riscv64-elf and riscv32-elf) with no
regressions.

	PR target/70557
gcc/
	* config/riscv/riscv.md (movdi_32bit): Add "J" constraint to allow storing 0
	directly to memory.
---

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a5b3abbe5d4..92fe7c7741a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2501,8 +2501,8 @@
 })
 
 (define_insn "*movdi_32bit"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,  *f,*f,*r,*f,*m,r")
-	(match_operand:DI 1 "move_operand"         " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,  *f,*f,*r,*f,*m,r")
+	(match_operand:DI 1 "move_operand"         " r,i,m,rJ,*J*r,*m,*f,*f,*f,vp"))]
   "!TARGET_64BIT
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"