From: Greg Kroah-Hartman Date: Fri, 4 Aug 2023 10:27:07 +0000 (+0200) Subject: 5.4-stable patches X-Git-Tag: v4.14.321~77 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c783417cf0eaeade4dfed60bb70a3479a8be97f6;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch arm64-fix-bit-shifting-ub-in-the-midr_cpu_model-macro.patch --- diff --git a/queue-5.4/arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch b/queue-5.4/arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch new file mode 100644 index 00000000000..3fda29c49e4 --- /dev/null +++ b/queue-5.4/arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch @@ -0,0 +1,74 @@ +From 0e5d5ae837c8ce04d2ddb874ec5f920118bd9d31 Mon Sep 17 00:00:00 2001 +From: D Scott Phillips +Date: Mon, 10 Oct 2022 19:21:40 -0700 +Subject: arm64: Add AMPERE1 to the Spectre-BHB affected list + +From: D Scott Phillips + +commit 0e5d5ae837c8ce04d2ddb874ec5f920118bd9d31 upstream. + +Per AmpereOne erratum AC03_CPU_12, "Branch history may allow control of +speculative execution across software contexts," the AMPERE1 core needs the +bhb clearing loop to mitigate Spectre-BHB, with a loop iteration count of +11. + +Signed-off-by: D Scott Phillips +Link: https://lore.kernel.org/r/20221011022140.432370-1-scott@os.amperecomputing.com +Reviewed-by: James Morse +Signed-off-by: Catalin Marinas +Signed-off-by: Ovidiu Panait +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cputype.h | 4 ++++ + arch/arm64/kernel/cpu_errata.c | 6 ++++++ + 2 files changed, 10 insertions(+) + +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -59,6 +59,7 @@ + #define ARM_CPU_IMP_NVIDIA 0x4E + #define ARM_CPU_IMP_FUJITSU 0x46 + #define ARM_CPU_IMP_HISI 0x48 ++#define ARM_CPU_IMP_AMPERE 0xC0 + + #define ARM_CPU_PART_AEM_V8 0xD0F + #define ARM_CPU_PART_FOUNDATION 0xD00 +@@ -101,6 +102,8 @@ + + #define HISI_CPU_PART_TSV110 0xD01 + ++#define AMPERE_CPU_PART_AMPERE1 0xAC3 ++ + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) + #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) + #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +@@ -131,6 +134,7 @@ + #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) + #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) + #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) ++#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) + + /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ + #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -1145,6 +1145,10 @@ u8 spectre_bhb_loop_affected(int scope) + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + {}, + }; ++ static const struct midr_range spectre_bhb_k11_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_AMPERE1), ++ {}, ++ }; + static const struct midr_range spectre_bhb_k8_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), +@@ -1155,6 +1159,8 @@ u8 spectre_bhb_loop_affected(int scope) + k = 32; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) + k = 24; ++ else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list)) ++ k = 11; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) + k = 8; + diff --git a/queue-5.4/arm64-fix-bit-shifting-ub-in-the-midr_cpu_model-macro.patch b/queue-5.4/arm64-fix-bit-shifting-ub-in-the-midr_cpu_model-macro.patch new file mode 100644 index 00000000000..38af9e859b8 --- /dev/null +++ b/queue-5.4/arm64-fix-bit-shifting-ub-in-the-midr_cpu_model-macro.patch @@ -0,0 +1,46 @@ +From 8ec8490a1950efeccb00967698cf7cb2fcd25ca7 Mon Sep 17 00:00:00 2001 +From: D Scott Phillips +Date: Wed, 2 Nov 2022 09:01:06 -0700 +Subject: arm64: Fix bit-shifting UB in the MIDR_CPU_MODEL() macro + +From: D Scott Phillips + +commit 8ec8490a1950efeccb00967698cf7cb2fcd25ca7 upstream. + +CONFIG_UBSAN_SHIFT with gcc-5 complains that the shifting of +ARM_CPU_IMP_AMPERE (0xC0) into bits [31:24] by MIDR_CPU_MODEL() is +undefined behavior. Well, sort of, it actually spells the error as: + + arch/arm64/kernel/proton-pack.c: In function 'spectre_bhb_loop_affected': + arch/arm64/include/asm/cputype.h:44:2: error: initializer element is not constant + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + ^ + +This isn't an issue for other Implementor codes, as all the other codes +have zero in the top bit and so are representable as a signed int. + +Cast the implementor code to unsigned in MIDR_CPU_MODEL to remove the +undefined behavior. + +Fixes: 0e5d5ae837c8 ("arm64: Add AMPERE1 to the Spectre-BHB affected list") +Reported-by: Geert Uytterhoeven +Signed-off-by: D Scott Phillips +Link: https://lore.kernel.org/r/20221102160106.1096948-1-scott@os.amperecomputing.com +Signed-off-by: Catalin Marinas +Signed-off-by: Ovidiu Panait +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cputype.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -41,7 +41,7 @@ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + + #define MIDR_CPU_MODEL(imp, partnum) \ +- (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ ++ ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + diff --git a/queue-5.4/series b/queue-5.4/series index 6b82430a0c8..461fb807747 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -86,3 +86,5 @@ btrfs-qgroup-return-enotconn-instead-of-einval-when-quotas-are-not-enabled.patch btrfs-fix-race-between-quota-disable-and-quota-assign-ioctls.patch net-sched-sch_qfq-account-for-stab-overhead-in-qfq_enqueue.patch asoc-cs42l51-fix-driver-to-properly-autoload-with-automatic-module-loading.patch +arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch +arm64-fix-bit-shifting-ub-in-the-midr_cpu_model-macro.patch