From: Florian Krohm <florian@eich-krohm.de>
Date: Wed, 11 Sep 2013 18:43:26 +0000 (+0000)
Subject: Clarify wording.
X-Git-Tag: svn/VALGRIND_3_9_0~150
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c8b6aee25e5ab46ab09a784e23cee0ab23dd8fd3;p=thirdparty%2Fvalgrind.git

Clarify wording.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13541
---

diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index 3f49de95fa..1f47a357f7 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -713,7 +713,7 @@ Addr setup_client_stack( void*  init_sp,
             if (auxv->u.a_val > 0) {
                VG_(machine_ppc32_set_clszB)( auxv->u.a_val );
                VG_(debugLog)(2, "initimg", 
-                                "PPC32 cache line size %u (type %u)\n", 
+                                "PPC32 icache line size %u (type %u)\n", 
                                 (UInt)auxv->u.a_val, (UInt)auxv->a_type );
             }
 #           elif defined(VGP_ppc64_linux)
@@ -721,7 +721,7 @@ Addr setup_client_stack( void*  init_sp,
             if (auxv->u.a_val > 0) {
                VG_(machine_ppc64_set_clszB)( auxv->u.a_val );
                VG_(debugLog)(2, "initimg", 
-                                "PPC64 cache line size %u (type %u)\n", 
+                                "PPC64 icache line size %u (type %u)\n", 
                                 (UInt)auxv->u.a_val, (UInt)auxv->a_type );
             }
 #           endif
diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
index 2fd5f07ffb..2f9869dc35 100644
--- a/coregrind/m_machine.c
+++ b/coregrind/m_machine.c
@@ -1518,7 +1518,7 @@ Bool VG_(machine_get_hwcaps)( void )
 #endif
 }
 
-/* Notify host cpu cache line size. */
+/* Notify host cpu instruction cache line size. */
 #if defined(VGA_ppc32)
 void VG_(machine_ppc32_set_clszB)( Int szB )
 {
@@ -1536,7 +1536,7 @@ void VG_(machine_ppc32_set_clszB)( Int szB )
 #endif
 
 
-/* Notify host cpu cache line size. */
+/* Notify host cpu instruction cache line size. */
 #if defined(VGA_ppc64)
 void VG_(machine_ppc64_set_clszB)( Int szB )
 {