From: Andrea Corallo Date: Mon, 28 Nov 2022 16:09:16 +0000 (+0100) Subject: arm: improve tests and fix vnegq* X-Git-Tag: basepoints/gcc-14~1856 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c8cb7e062664e5db5969de4239be513dfd6ab1d1;p=thirdparty%2Fgcc.git arm: improve tests and fix vnegq* gcc/ChangeLog: * config/arm/mve.md (mve_vnegq_f, mve_vnegq_s): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vnegq_f16.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vnegq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise. * gcc.target/arm/simd/mve-vneg.c: Update test. * gcc.target/arm/simd/mve-vshr.c: Likewise --- diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 272853700910..7767f945a72b 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -252,7 +252,7 @@ (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vneg.f%# %q0, %q1" + "vneg.f%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) @@ -401,7 +401,7 @@ (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vneg.s%# %q0, %q1" + "vneg.s%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c index 9572c140d7ea..9853cf6e6dd0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c @@ -1,13 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a) { return vnegq_f16 (a); } -/* { dg-final { scan-assembler "vneg.f16" } } */ + +/* +**foo1: +** ... +** vneg.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +float16x8_t +foo1 (float16x8_t a) +{ + return vnegq (a); +} + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c index be73cc0c5f5f..489cfc760ba7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c @@ -1,13 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a) { return vnegq_f32 (a); } -/* { dg-final { scan-assembler "vneg.f32" } } */ + +/* +**foo1: +** ... +** vneg.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +float32x4_t +foo1 (float32x4_t a) +{ + return vnegq (a); +} + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c index 0d917b80cd73..c8b307ea50e9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) { return vnegq_m_f16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) { return vnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c index f1c0e9a99b05..a530a05e644f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) { return vnegq_m_f32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) { return vnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c index 9a945ee62a37..46d6e794dbe1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vnegq_m_s16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c index 811f1df05658..5fb1f5c2a4cc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vnegq_m_s32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c index 430ebc737835..868a96808587 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vnegq_m_s8 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vnegq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c index a47f9b3423e1..3b518c8e0f5d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c @@ -1,21 +1,41 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a) { return vnegq_s16 (a); } -/* { dg-final { scan-assembler "vneg.s16" } } */ +/* +**foo1: +** ... +** vneg.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a) { return vnegq (a); } -/* { dg-final { scan-assembler "vneg.s16" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c index 50401f53bd7a..f8682575892d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c @@ -1,21 +1,41 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a) { return vnegq_s32 (a); } -/* { dg-final { scan-assembler "vneg.s32" } } */ +/* +**foo1: +** ... +** vneg.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a) { return vnegq (a); } -/* { dg-final { scan-assembler "vneg.s32" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c index fd5de3dab56a..1be5901740e8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a) { return vnegq_s8 (a); } -/* { dg-final { scan-assembler "vneg.s8" } } */ +/* +**foo1: +** ... +** vneg.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a) { return vnegq (a); } -/* { dg-final { scan-assembler "vneg.s8" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c index e7af36691dcb..c10d6d2aebfa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, mve_pred16_t p) { return vnegq_x_f16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, mve_pred16_t p) { return vnegq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c index d9c3818855a9..0ee5ecc8262e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, mve_pred16_t p) { return vnegq_x_f32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, mve_pred16_t p) { return vnegq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c index 16f1fa452ceb..d774a055d72d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, mve_pred16_t p) { return vnegq_x_s16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, mve_pred16_t p) { return vnegq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c index d74683c6f240..77bf1a67cfe0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, mve_pred16_t p) { return vnegq_x_s32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, mve_pred16_t p) { return vnegq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c index eda4c7fcf7e1..ca44512e37a5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c @@ -1,22 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, mve_pred16_t p) { return vnegq_x_s8 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vnegt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vnegt.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, mve_pred16_t p) { return vnegq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c index 7945a060e25f..1379cae579f4 100644 --- a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c @@ -45,8 +45,8 @@ FUNC(f, float, 16, 8, -, vneg) /* MVE has only 128-bit vectors, so we can vectorize only half of the functions above. */ -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */ -/* { dg-final { scan-assembler-times {vneg.f[0-9]+ q[0-9]+, q[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {vneg.f[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {vldr[bhw].[0-9]+\tq[0-9]+} 8 } } */ /* { dg-final { scan-assembler-times {vstr[bhw].[0-9]+\tq[0-9]+} 8 } } */ /* { dg-final { scan-assembler-not {orr\tr[0-9]+, r[0-9]+, r[0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c index d4258e9fefeb..8c7adef9ed8f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vshr.c @@ -58,7 +58,7 @@ FUNC_IMM(u, uint, 8, 16, >>, vshrimm) /* Vector right shifts use vneg and left shifts. */ /* { dg-final { scan-assembler-times {vshl.s[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 3 } } */ -/* { dg-final { scan-assembler-times {vneg.s[0-9]+ q[0-9]+, q[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {vneg.s[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */ /* Shift by immediate. */