From: GCC Administrator Date: Fri, 2 Oct 2020 00:17:05 +0000 (+0000) Subject: Daily bump. X-Git-Tag: releases/gcc-10.3.0~822 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c9176d120de0e181812858ff5fcfe2715859c196;p=thirdparty%2Fgcc.git Daily bump. --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 41854a4ea744..adea79980469 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,100 @@ +2020-10-01 Martin Liska + + Backported from master: + 2020-09-25 Martin Liska + + PR gcov-profile/64636 + * value-prof.c (stream_out_histogram_value): Allow negative + values for HIST_TYPE_IOR. + +2020-10-01 Martin Liska + + Backported from master: + 2020-09-29 Martin Liska + + PR tree-optimization/96979 + * tree-switch-conversion.c (jump_table_cluster::can_be_handled): + Make a fast bail out. + (bit_test_cluster::can_be_handled): Likewise here. + * tree-switch-conversion.h (get_range): Use wi::to_wide instead + of a folding. + +2020-10-01 Martin Liska + + Backported from master: + 2020-09-23 Martin Liska + + PR gcov-profile/97069 + * profile.c (branch_prob): Line number must be at least 1. + +2020-10-01 Michael Davidsaver + + * config/i386/t-rtems: Change from mtune to march when building + multilibs. The mtune argument tunes or optimizes for a specific + CPU model but does not ensure the generated code is appropriate + for the CPU model. Prior to this patch, i386 compatible code + was always generated but tuned for later models. + +2020-10-01 Srinath Parvathaneni + + Backported from master: + 2020-09-30 Srinath Parvathaneni + + PR target/96795 + * config/arm/arm_mve.h (__ARM_mve_coerce2): Define. + (__arm_vaddq): Correct the scalar argument. + (__arm_vaddq_m): Likewise. + (__arm_vaddq_x): Likewise. + (__arm_vcmpeqq_m): Likewise. + (__arm_vcmpeqq): Likewise. + (__arm_vcmpgeq_m): Likewise. + (__arm_vcmpgeq): Likewise. + (__arm_vcmpgtq_m): Likewise. + (__arm_vcmpgtq): Likewise. + (__arm_vcmpleq_m): Likewise. + (__arm_vcmpleq): Likewise. + (__arm_vcmpltq_m): Likewise. + (__arm_vcmpltq): Likewise. + (__arm_vcmpneq_m): Likewise. + (__arm_vcmpneq): Likewise. + (__arm_vfmaq_m): Likewise. + (__arm_vfmaq): Likewise. + (__arm_vfmasq_m): Likewise. + (__arm_vfmasq): Likewise. + (__arm_vmaxnmavq): Likewise. + (__arm_vmaxnmavq_p): Likewise. + (__arm_vmaxnmvq): Likewise. + (__arm_vmaxnmvq_p): Likewise. + (__arm_vminnmavq): Likewise. + (__arm_vminnmavq_p): Likewise. + (__arm_vminnmvq): Likewise. + (__arm_vminnmvq_p): Likewise. + (__arm_vmulq_m): Likewise. + (__arm_vmulq): Likewise. + (__arm_vmulq_x): Likewise. + (__arm_vsetq_lane): Likewise. + (__arm_vsubq_m): Likewise. + (__arm_vsubq): Likewise. + (__arm_vsubq_x): Likewise. + +2020-10-01 Jakub Jelinek + + Backported from master: + 2020-10-01 Jakub Jelinek + + * config/s390/s390.c (s390_atomic_assign_expand_fenv): Use + TARGET_EXPR instead of MODIFY_EXPR for the first assignments to + fenv_var and old_fpc. Formatting fixes. + +2020-10-01 Joel Hutton + + Backported from master: + 2020-09-30 Joel Hutton + + PR target/96827 + * tree-vect-slp.c (vect_analyze_slp): Do not call + vect_attempt_slp_rearrange_stmts for vector constructors. + 2020-09-30 Jim Wilson PR bootstrap/97183 diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index c5ffab195593..4d58d2f285ca 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20201001 +20201002 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 77d728023d6f..d7d013974e11 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,110 @@ +2020-10-01 Martin Liska + + Backported from master: + 2020-09-29 Martin Liska + + PR tree-optimization/96979 + * g++.dg/tree-ssa/pr96979.C: New test. + +2020-10-01 Martin Liska + + Backported from master: + 2020-09-23 Martin Liska + + PR gcov-profile/97069 + * g++.dg/gcov/pr97069.C: New test. + +2020-10-01 H.J. Lu + + Backported from master: + 2020-09-30 H.J. Lu + + PR target/96827 + * gcc.target/i386/pr96827.c: New test. + +2020-10-01 Srinath Parvathaneni + + Backported from master: + 2020-09-30 Srinath Parvathaneni + + PR target/96795 + * gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: New Test. + * gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Likewise. + * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Likewise. + +2020-10-01 Joel Hutton + + Backported from master: + 2020-09-30 Joel Hutton + + PR target/96827 + * gcc.dg/vect/bb-slp-49.c: New test. + 2020-09-30 H.J. Lu Backported from master: