From: Julian Seward Date: Sat, 30 Oct 2004 20:40:03 +0000 (+0000) Subject: Make addrcheck work again, including regparm. X-Git-Tag: svn/VALGRIND_3_0_1^2~871 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c94d69a5131c94428190df8090e10ab1c4ba593c;p=thirdparty%2Fvalgrind.git Make addrcheck work again, including regparm. git-svn-id: svn://svn.valgrind.org/vex/trunk@463 --- diff --git a/VEX/head20041019/addrcheck/ac_main.c b/VEX/head20041019/addrcheck/ac_main.c index 5445ee042c..70f75e5b35 100644 --- a/VEX/head20041019/addrcheck/ac_main.c +++ b/VEX/head20041019/addrcheck/ac_main.c @@ -715,34 +715,34 @@ static __inline__ void ac_helperc_ACCESS1 ( Addr a, Bool isWrite ) # endif } -//REGPARM(1) +REGPARM(1) static void ac_helperc_LOAD4 ( Addr a ) { ac_helperc_ACCESS4 ( a, /*isWrite*/False ); } -//REGPARM(1) +REGPARM(1) static void ac_helperc_STORE4 ( Addr a ) { ac_helperc_ACCESS4 ( a, /*isWrite*/True ); } -//REGPARM(1) +REGPARM(1) static void ac_helperc_LOAD2 ( Addr a ) { ac_helperc_ACCESS2 ( a, /*isWrite*/False ); } -//REGPARM(1) +REGPARM(1) static void ac_helperc_STORE2 ( Addr a ) { ac_helperc_ACCESS2 ( a, /*isWrite*/True ); } -//REGPARM(1) +REGPARM(1) static void ac_helperc_LOAD1 ( Addr a ) { ac_helperc_ACCESS1 ( a, /*isWrite*/False ); } -//REGPARM(1) +REGPARM(1) static void ac_helperc_STORE1 ( Addr a ) { ac_helperc_ACCESS1 ( a, /*isWrite*/True ); @@ -912,13 +912,13 @@ void ac_fpu_ACCESS_check ( Addr addr, Int size, Bool isWrite ) # endif } -//REGPARM(2) +REGPARM(2) static void ac_helperc_LOADN ( Addr addr, Int size ) { ac_fpu_ACCESS_check ( addr, size, /*isWrite*/False ); } -//REGPARM(2) +REGPARM(2) static void ac_helperc_STOREN ( Addr addr, Int size ) { ac_fpu_ACCESS_check ( addr, size, /*isWrite*/True ); @@ -982,11 +982,11 @@ IRBB* SK_(instrument)(IRBB* bb_in, VexGuestLayoutInfo* layout) Int i; Int sz; - Char* helper; - IRStmt* st; - IRExpr* data; - IRExpr* addr; - Bool needSz; + IRCallee* helper; + IRStmt* st; + IRExpr* data; + IRExpr* addr; + Bool needSz; /* Set up BB */ IRBB* bb = emptyIRBB(); @@ -1010,10 +1010,18 @@ IRBB* SK_(instrument)(IRBB* bb_in, VexGuestLayoutInfo* layout) sz = sizeofIRType(data->Iex.LDle.ty); needSz = False; switch (sz) { - case 4: helper = "ac_helperc_LOAD4"; break; - case 2: helper = "ac_helperc_LOAD2"; break; - case 1: helper = "ac_helperc_LOAD1"; break; - default: helper = "ac_helperc_LOADN"; needSz = True; break; + case 4: helper = mkIRCallee(1, + "ac_helperc_LOAD4", + (HWord)&ac_helperc_LOAD4); break; + case 2: helper = mkIRCallee(1, + "ac_helperc_LOAD2", + (HWord)&ac_helperc_LOAD2); break; + case 1: helper = mkIRCallee(1, + "ac_helperc_LOAD1", + (HWord)&ac_helperc_LOAD1); break; + default: helper = mkIRCallee(2, "ac_helperc_LOADN", + (HWord)&ac_helperc_LOADN); + needSz = True; break; } if (needSz) { addStmtToIRBB( @@ -1041,10 +1049,18 @@ IRBB* SK_(instrument)(IRBB* bb_in, VexGuestLayoutInfo* layout) sz = sizeofIRType(typeOfIRExpr(bb_in->tyenv, data)); needSz = False; switch (sz) { - case 4: helper = "ac_helperc_STORE4"; break; - case 2: helper = "ac_helperc_STORE2"; break; - case 1: helper = "ac_helperc_STORE1"; break; - default: helper = "ac_helperc_STOREN"; needSz = True; break; + case 4: helper = mkIRCallee(1, + "ac_helperc_STORE4", + (HWord)&ac_helperc_STORE4); break; + case 2: helper = mkIRCallee(1, + "ac_helperc_STORE2", + (HWord)&ac_helperc_STORE2); break; + case 1: helper = mkIRCallee(1, + "ac_helperc_STORE1", + (HWord)&ac_helperc_STORE1); break; + default: helper = mkIRCallee(2, "ac_helperc_STOREN", + (HWord)&ac_helperc_STOREN); + needSz = True; break; } if (needSz) { addStmtToIRBB( @@ -1097,131 +1113,6 @@ IRBB* SK_(instrument)(IRBB* bb_in, VexGuestLayoutInfo* layout) return bb; } -#if 0 -------------------- - cb = VG_(setup_UCodeBlock)(cb_in); - - for (i = 0; i < VG_(get_num_instrs)(cb_in); i++) { - - t_addr = t_size = INVALID_TEMPREG; - u_in = VG_(get_instr)(cb_in, i); - - switch (u_in->opcode) { - case NOP: case LOCK: case CALLM_E: case CALLM_S: - break; - - /* For memory-ref instrs, copy the data_addr into a temporary - * to be passed to the helper at the end of the instruction. - */ - case LOAD: - switch (u_in->size) { - case 4: helper = (Addr)ac_helperc_LOAD4; break; - case 2: helper = (Addr)ac_helperc_LOAD2; break; - case 1: helper = (Addr)ac_helperc_LOAD1; break; - default: VG_(skin_panic) - ("addrcheck::SK_(instrument):LOAD"); - } - uInstr1(cb, CCALL, 0, TempReg, u_in->val1); - uCCall (cb, helper, 1, 1, False ); - VG_(copy_UInstr)(cb, u_in); - break; - - case STORE: - switch (u_in->size) { - case 4: helper = (Addr)ac_helperc_STORE4; break; - case 2: helper = (Addr)ac_helperc_STORE2; break; - case 1: helper = (Addr)ac_helperc_STORE1; break; - default: VG_(skin_panic) - ("addrcheck::SK_(instrument):STORE"); - } - uInstr1(cb, CCALL, 0, TempReg, u_in->val2); - uCCall (cb, helper, 1, 1, False ); - VG_(copy_UInstr)(cb, u_in); - break; - - case SSE3ag_MemRd_RegWr: - sk_assert(u_in->size == 4 || u_in->size == 8); - helper = (Addr)ac_fpu_READ_check; - goto do_Access_ARG1; - do_Access_ARG1: - sk_assert(u_in->tag1 == TempReg); - t_addr = u_in->val1; - t_size = newTemp(cb); - uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_size); - uLiteral(cb, u_in->size); - uInstr2(cb, CCALL, 0, TempReg, t_addr, TempReg, t_size); - uCCall(cb, helper, 2, 2, False ); - VG_(copy_UInstr)(cb, u_in); - break; - - case MMX2_MemRd: - sk_assert(u_in->size == 4 || u_in->size == 8); - helper = (Addr)ac_fpu_READ_check; - goto do_Access_ARG2; - case MMX2_MemWr: - sk_assert(u_in->size == 4 || u_in->size == 8); - helper = (Addr)ac_fpu_WRITE_check; - goto do_Access_ARG2; - case FPU_R: - helper = (Addr)ac_fpu_READ_check; - goto do_Access_ARG2; - case FPU_W: - helper = (Addr)ac_fpu_WRITE_check; - goto do_Access_ARG2; - do_Access_ARG2: - sk_assert(u_in->tag2 == TempReg); - t_addr = u_in->val2; - t_size = newTemp(cb); - uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_size); - uLiteral(cb, u_in->size); - uInstr2(cb, CCALL, 0, TempReg, t_addr, TempReg, t_size); - uCCall(cb, helper, 2, 2, False ); - VG_(copy_UInstr)(cb, u_in); - break; - - case MMX2a1_MemRd: - case SSE3a_MemRd: - case SSE2a_MemRd: - case SSE3a1_MemRd: - case SSE2a1_MemRd: - helper = (Addr)ac_fpu_READ_check; - goto do_Access_ARG3; - case SSE2a_MemWr: - case SSE3a_MemWr: - helper = (Addr)ac_fpu_WRITE_check; - goto do_Access_ARG3; - do_Access_ARG3: - sk_assert(u_in->size == 4 || u_in->size == 8 - || u_in->size == 16 || u_in->size == 512); - sk_assert(u_in->tag3 == TempReg); - t_addr = u_in->val3; - t_size = newTemp(cb); - uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_size); - uLiteral(cb, u_in->size); - uInstr2(cb, CCALL, 0, TempReg, t_addr, TempReg, t_size); - uCCall(cb, helper, 2, 2, False ); - VG_(copy_UInstr)(cb, u_in); - break; - - case SSE3e1_RegRd: - case SSE3e_RegWr: - case SSE3g1_RegWr: - case SSE5: - case SSE3g_RegWr: - case SSE3e_RegRd: - case SSE4: - case SSE3: - default: - VG_(copy_UInstr)(cb, u_in); - break; - } - } - - VG_(free_UCodeBlock)(cb_in); - return cb; -} -#endif - /*------------------------------------------------------------*/ /*--- Detecting leaked (unreachable) malloc'd blocks. ---*/ diff --git a/VEX/head20041019/coregrind/core.h b/VEX/head20041019/coregrind/core.h index b794302819..d351a97f7e 100644 --- a/VEX/head20041019/coregrind/core.h +++ b/VEX/head20041019/coregrind/core.h @@ -1336,7 +1336,7 @@ extern Bool VG_(seg_overlaps)(const Segment *s, Addr ptr, UInt size); extern void VG_(pad_address_space)(void); extern void VG_(unpad_address_space)(void); -extern //REGPARM(1) +extern REGPARM(1) void VG_(unknown_esp_update) ( Addr new_ESP ); /* --------------------------------------------------------------------- diff --git a/VEX/head20041019/coregrind/valgrind.vs b/VEX/head20041019/coregrind/valgrind.vs index f964bab73f..02865d2503 100644 --- a/VEX/head20041019/coregrind/valgrind.vs +++ b/VEX/head20041019/coregrind/valgrind.vs @@ -10,6 +10,7 @@ VALGRIND_2.1 { *IRBB*; *IRDirty*; *IRType*; + *IRCallee*; LibVEX_Alloc; local: diff --git a/VEX/head20041019/coregrind/vg_memory.c b/VEX/head20041019/coregrind/vg_memory.c index 31d328f309..637dc6f0a7 100644 --- a/VEX/head20041019/coregrind/vg_memory.c +++ b/VEX/head20041019/coregrind/vg_memory.c @@ -674,7 +674,7 @@ Segment *VG_(next_segment)(Segment *s) /* This function gets called if new_mem_stack and/or die_mem_stack are tracked by the tool, and one of the specialised cases (eg. new_mem_stack_4) isn't used in preference */ -//REGPARM(1) +REGPARM(1) void VG_(unknown_esp_update)(Addr new_SP) { Addr old_SP = BASEBLOCK_STACK_PTR; //VG_(get_archreg)(R_STACK_PTR); diff --git a/VEX/head20041019/coregrind/vg_translate.c b/VEX/head20041019/coregrind/vg_translate.c index 26af4a9781..9150c5f1b7 100644 --- a/VEX/head20041019/coregrind/vg_translate.c +++ b/VEX/head20041019/coregrind/vg_translate.c @@ -1405,8 +1405,11 @@ IRBB* vg_SP_update_pass ( IRBB* bb_in, VexGuestLayoutInfo* layout ) /* I don't know if it's really necessary to say that the call reads the stack pointer. But anyway, we do. */ - dcall = unsafeIRDirty_0_N( "VG_(unknown_esp_update)", - mkIRExprVec_1(st->Ist.Put.data) ); + dcall = unsafeIRDirty_0_N( + mkIRCallee(1, "VG_(unknown_esp_update)", + (HWord)&VG_(unknown_esp_update)), + mkIRExprVec_1(st->Ist.Put.data) + ); dcall->nFxState = 1; dcall->fxState[0].fx = Ifx_Read; dcall->fxState[0].offset = layout->offset_SP; @@ -1460,15 +1463,6 @@ void log_bytes ( Char* bytes, Int nbytes ) 'tid' is the identity of the thread needing this block. */ -/* HACK HACK HACK */ -static HWord hacky_findhelper ( Char* function_name ) -{ - if (0 == VG_(strcmp)(function_name, "VG_(unknown_esp_update)")) - return (HWord) & VG_(unknown_esp_update); - return SK_(tool_findhelper)( function_name ); -} - - Bool VG_(translate) ( ThreadId tid, Addr orig_addr, Bool debugging_translation ) { @@ -1567,7 +1561,6 @@ Bool VG_(translate) ( ThreadId tid, Addr orig_addr, VG_(need_to_handle_esp_assignment)() ? vg_SP_update_pass : NULL, - hacky_findhelper, /* SK_(tool_findhelper), */ NULL, VG_(clo_trace_codegen) );