From: wilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 19 Sep 2019 16:51:08 +0000 (+0000)
Subject: [ARM] Simplify logical DImode iterators
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=c9ad5cc4eae6d8ad22a844254ffc0d3a7073b25e;p=thirdparty%2Fgcc.git

[ARM] Simplify logical DImode iterators

Further simplify the logical DImode expander using code iterator and
obtab attributes.  This avoids adding unnecessary code_attr entries.

    gcc/
	* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
	* config/arm/iterators.md (optab): Add and, ior, xor entries.
	(logical_op): Remove code attribute.
	(logical_OP): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@275970 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ac055ef27a53..3be2b55523b6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-09-19  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
+	* config/arm/iterators.md (optab): Add and, ior, xor entries.
+	(logical_op): Remove code attribute.
+	(logical_OP): Likewise.
+
 2019-09-19  Martin Liska  <mliska@suse.cz>
 
 	* ipa-icf.c (sort_congruence_class_groups_by_decl_uid):
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d54082b13dd7..d607f88cb05f 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2039,16 +2039,16 @@
 ; operands or complex immediates, which leads to fewer LDRD/STRD instructions.
 ; So an explicit expander is needed to generate better code.
 
-(define_expand "<logical_op>di3"
+(define_expand "<LOGICAL:optab>di3"
   [(set (match_operand:DI	  0 "s_register_operand")
 	(LOGICAL:DI (match_operand:DI 1 "s_register_operand")
-		    (match_operand:DI 2 "arm_<logical_op>di_operand")))]
+		    (match_operand:DI 2 "arm_<optab>di_operand")))]
   "TARGET_32BIT"
   {
-      rtx low  = simplify_gen_binary (<logical_OP>, SImode,
+      rtx low  = simplify_gen_binary (<CODE>, SImode,
 				      gen_lowpart (SImode, operands[1]),
 				      gen_lowpart (SImode, operands[2]));
-      rtx high = simplify_gen_binary (<logical_OP>, SImode,
+      rtx high = simplify_gen_binary (<CODE>, SImode,
 				      gen_highpart (SImode, operands[1]),
 				      gen_highpart_mode (SImode, DImode,
 							 operands[2]));
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5e3299e85081..2d8ef3f5fbd5 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -287,9 +287,6 @@
 
 (define_code_attr vfml_op [(plus "a") (minus "s")])
 
-(define_code_attr logical_op [(ior "ior") (xor "xor") (and "and")])
-(define_code_attr logical_OP [(ior "IOR") (xor "XOR") (and "AND")])
-
 ;;----------------------------------------------------------------------------
 ;; Int iterators
 ;;----------------------------------------------------------------------------
@@ -797,7 +794,14 @@
                 (umax "u")])
 
 (define_code_attr cnb [(ltu "CC_C") (geu "CC")])
-(define_code_attr optab [(ltu "ltu") (geu "geu")])
+
+;; Map rtl operator codes to optab names
+(define_code_attr optab
+ [(ltu "ltu")
+  (geu "geu")
+  (and "and")
+  (ior "ior")
+  (xor "xor")])
 
 ;; Assembler mnemonics for signedness of widening operations.
 (define_code_attr US [(sign_extend "s") (zero_extend "u")])