From: Konrad Dybcio Date: Thu, 26 Jun 2025 09:02:38 +0000 (+0200) Subject: soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=caf5ad18a2b49e3b20b1dc65e928851d409bcd1c;p=thirdparty%2Fkernel%2Flinux.git soc: qcom: ubwc: Fix SM6125's ubwc_swizzle value The value of 7 (a.k.a. GENMASK(2, 0), a.k.a. disabling levels 1-3 of swizzling) is what we want on this platform (and others with a UBWC 1.0 encoder). Fix it to make mesa happy (the hardware doesn't care about the 2 higher bits, as they weren't consumed on this platform). Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/660980/ Signed-off-by: Rob Clark --- diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 18a853a3f76cc..3eb2f2118e5d1 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -103,7 +103,7 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { static const struct qcom_ubwc_cfg_data sm6125_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_3_0, - .ubwc_swizzle = 1, + .ubwc_swizzle = 7, .highest_bank_bit = 14, };