From: Kyrylo Tkachov Date: Tue, 2 Sep 2025 07:43:14 +0000 (-0700) Subject: aarch64: PR target/121749: Use correct predicate for narrowing shift amounts X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cb508e54140687a50790059fac548d87515df6be;p=thirdparty%2Fgcc.git aarch64: PR target/121749: Use correct predicate for narrowing shift amounts With g:d20b2ad845876eec0ee80a3933ad49f9f6c4ee30 the narrowing shift instructions are now represented with standard RTL and more merging optimisations occur. This exposed a wrong predicate for the shift amount operand. The shift amount is the number of bits of the narrow destination, not the input sources. Correct this by using the vn_mode attribute when specifying the predicate, which exists for this purpose. I've spotted a few more narrowing shift patterns that need the restriction, so they are updated as well. Bootstrapped and tested on aarch64-none-linux-gnu. Signed-off-by: Kyrylo Tkachov gcc/ PR target/121749 * config/aarch64/aarch64-simd.md (aarch64_shrn_n): Use aarch64_simd_shift_imm_offset_ instead of aarch64_simd_shift_imm_offset_ predicate. (aarch64_shrn_n VQN define_expand): Likewise. (*aarch64_rshrn_n_insn): Likewise. (aarch64_rshrn_n): Likewise. (aarch64_rshrn_n VQN define_expand): Likewise. (aarch64_sqshrun_n_insn): Likewise. (aarch64_sqshrun_n): Likewise. (aarch64_sqshrun_n VQN define_expand): Likewise. (aarch64_sqrshrun_n_insn): Likewise. (aarch64_sqrshrun_n): Likewise. (aarch64_sqrshrun_n): Likewise. * config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes. gcc/testsuite/ PR target/121749 * gcc.target/aarch64/simd/pr121749.c: New test. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 8b75c3d7f6d..c111dc2c7f7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -6731,7 +6731,7 @@ (SAT_TRUNC: (:SD_HSDI (match_operand:SD_HSDI 1 "register_operand" "w") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] "TARGET_SIMD" "shrn\t%0, %1, %2" [(set_attr "type" "neon_shift_imm_narrow_q")] @@ -6753,7 +6753,7 @@ (ALL_TRUNC: (:VQN (match_operand:VQN 1 "register_operand") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] "TARGET_SIMD" { operands[2] = aarch64_simd_gen_const_vector_dup (mode, @@ -6784,7 +6784,7 @@ (: (match_operand:SD_HSDI 1 "register_operand" "w")) (match_operand: 3 "aarch64_int_rnd_operand")) - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] "TARGET_SIMD && aarch64_const_vec_rnd_cst_p (operands[3], operands[2])" "rshrn\t%0, %1, %2" @@ -6799,7 +6799,7 @@ (: (match_operand:SD_HSDI 1 "register_operand")) (match_dup 3)) - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] "TARGET_SIMD" { /* Use this expander to create the rounding constant vector, which is @@ -6819,7 +6819,7 @@ (: (match_operand:VQN 1 "register_operand")) (match_dup 3)) - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_"))))] "TARGET_SIMD" { if ( == TRUNCATE @@ -6861,7 +6861,7 @@ (smax:SD_HSDI (ashiftrt:SD_HSDI (match_operand:SD_HSDI 1 "register_operand" "w") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) (const_int 0)) (const_int )))] "TARGET_SIMD" @@ -6872,7 +6872,7 @@ (define_expand "aarch64_sqshrun_n" [(match_operand: 0 "register_operand") (match_operand:SD_HSDI 1 "register_operand") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")] "TARGET_SIMD" { rtx dst = gen_reg_rtx (mode); @@ -6890,7 +6890,7 @@ (smax:VQN (ashiftrt:VQN (match_operand:VQN 1 "register_operand") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) (match_dup 3)) (match_dup 4))))] "TARGET_SIMD" @@ -6932,7 +6932,7 @@ (sign_extend: (match_operand:SD_HSDI 1 "register_operand" "w")) (match_operand: 3 "aarch64_int_rnd_operand")) - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) (const_int 0)) (const_int )))] "TARGET_SIMD @@ -6944,7 +6944,7 @@ (define_expand "aarch64_sqrshrun_n" [(match_operand: 0 "register_operand") (match_operand:SD_HSDI 1 "register_operand") - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")] + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")] "TARGET_SIMD" { int prec = GET_MODE_UNIT_PRECISION (mode); @@ -6967,7 +6967,7 @@ (sign_extend: (match_operand:VQN 1 "register_operand")) (match_dup 3)) - (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) + (match_operand:SI 2 "aarch64_simd_shift_imm_offset_")) (match_dup 4)) (match_dup 5))))] "TARGET_SIMD" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index b15e57843fe..7a6ea0d8d06 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2205,7 +2205,8 @@ (SI "si")]) ;; Like ve_mode but for the half-width modes. -(define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si")]) +(define_mode_attr vn_mode [(V8HI "qi") (V4SI "hi") (V2DI "si") (DI "si") + (SI "hi") (HI "qi")]) ;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c b/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c new file mode 100644 index 00000000000..c4e1a2d76cf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/pr121749.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include + +uint32_t +foo (uint64_t v0) +{ + return vqshrnd_n_u64 (vshrd_n_u64 (v0, 26), 7); +} +