From: Vivian Wang Date: Thu, 29 Jan 2026 01:56:09 +0000 (+0800) Subject: ALSA: hda/intel: Make MSI address limit based on the device DMA limit X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cb9b6f9d2be6bda1b0117b147df40f982ce06888;p=thirdparty%2Fkernel%2Flinux.git ALSA: hda/intel: Make MSI address limit based on the device DMA limit The hda/intel driver restricts the MSI message address for devices which do not advertise full 64-bit DMA address space support to 32-bit due to the former restrictions of the PCI/MSI code which only allowed either 32-bit or a full 64-bit address range. This does not work on platforms which have a MSI doorbell address above the 32-bit boundary but do not support the full 64 bit address range. The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based decision, which allows to describe the device limitations precisely. Convert the driver to provide the exact DMA address limitations to the PCI/MSI core. That allows devices which do not support the full 64-bit address space to work on platforms which have a MSI doorbell address above the 32-bit limit as long as it is within the hardware's addressable range. [ tglx: Massage changelog ] Signed-off-by: Vivian Wang Signed-off-by: Thomas Gleixner Acked-by: Takashi Iwai Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn --- diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c index c9542ebdf7e2b..a44de2306a2b7 100644 --- a/sound/hda/controllers/intel.c +++ b/sound/hda/controllers/intel.c @@ -1903,11 +1903,6 @@ static int azx_first_init(struct azx *chip) chip->gts_present = true; #endif - if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { - dev_dbg(card->dev, "Disabling 64bit MSI\n"); - pci->msi_addr_mask = DMA_BIT_MASK(32); - } - pci_set_master(pci); gcap = azx_readw(chip, GCAP); @@ -1958,6 +1953,11 @@ static int azx_first_init(struct azx *chip) dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); dma_set_max_seg_size(&pci->dev, UINT_MAX); + if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { + dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); + pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); + } + /* read number of streams from GCAP register instead of using * hardcoded value */