From: Pan Li Date: Wed, 2 Aug 2023 10:15:47 +0000 (+0800) Subject: RISC-V: Support RVV VFWSUB rounding mode intrinsic API X-Git-Tag: basepoints/gcc-15~7204 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cba9db950371e810e32e75425707beceb85bb0f0;p=thirdparty%2Fgcc.git RISC-V: Support RVV VFWSUB rounding mode intrinsic API This patch would like to support the rounding mode API for the VFWSUB for the below samples. * __riscv_vfwsub_vv_f64m2_rm * __riscv_vfwsub_vv_f64m2_rm_m * __riscv_vfwsub_vf_f64m2_rm * __riscv_vfwsub_vf_f64m2_rm_m * __riscv_vfwsub_wv_f64m2_rm * __riscv_vfwsub_wv_f64m2_rm_m * __riscv_vfwsub_wf_f64m2_rm * __riscv_vfwsub_wf_f64m2_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vfwsub frm. * config/riscv/riscv-vector-builtins-bases.h: Add declaration. * config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm): Add vfwsub function definitions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-widening-sub.c: New test. --- diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 981a4a7ede81..ddf694c771c7 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -317,6 +317,7 @@ public: /* Implements below instructions for frm - vfwadd + - vfwsub */ template class widen_binop_frm : public function_base @@ -2100,6 +2101,7 @@ static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj; static CONSTEXPR const widen_binop vfwadd_obj; static CONSTEXPR const widen_binop_frm vfwadd_frm_obj; static CONSTEXPR const widen_binop vfwsub_obj; +static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; static CONSTEXPR const binop
vfdiv_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; @@ -2330,6 +2332,7 @@ BASE (vfrsub_frm) BASE (vfwadd) BASE (vfwadd_frm) BASE (vfwsub) +BASE (vfwsub_frm) BASE (vfmul) BASE (vfdiv) BASE (vfrdiv) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index f9e1df5fe759..5800fca01697 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -150,6 +150,7 @@ extern const function_base *const vfrsub_frm; extern const function_base *const vfwadd; extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; +extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; extern const function_base *const vfmul; extern const function_base *const vfdiv; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 743205a9b97c..58a7224fe0c9 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -306,8 +306,12 @@ DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvv_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvf_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwv_ops) DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwf_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwv_ops) +DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwf_ops) // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvv_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c new file mode 100644 index 000000000000..4325cc510a7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_vv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_vv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfwsub_vf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwsub_vf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwsub_wv_f32m1_rm (vfloat64m2_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_wv_f64m2_rm (op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwsub_wv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_wv_f64m2_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwsub_wf_f32m1_rm (vfloat64m2_t op1, float32_t op2, size_t vl) { + return __riscv_vfwsub_wf_f64m2_rm (op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwsub_wf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t op1, float32_t op2, + size_t vl) { + return __riscv_vfwsub_wf_f64m2_rm_m (mask, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfwsub_vv_f64m2 (op1, op2, vl); +} + +vfloat64m2_t +test_vfwsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwsub_vv_f64m2_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwsub\.[vw][vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 10 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 8 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 8 } } */