From: Jiaxun Yang Date: Wed, 12 Jun 2024 08:54:33 +0000 (+0100) Subject: clocksource/drivers/mips-gic-timer: Refine rating computation X-Git-Tag: v6.11-rc1~228^2^2~7 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3;p=thirdparty%2Flinux.git clocksource/drivers/mips-gic-timer: Refine rating computation It is a good clocksource which usually go as fast as CPU core and have a low access latency, so raise the base of rating from Good to desired when we know that it has a stable frequency. Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level clock, also cap rating within current level. Signed-off-by: Jiaxun Yang Link: https://lore.kernel.org/r/20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com Signed-off-by: Daniel Lezcano --- diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index b3ae38f367205..7a03d94c028a9 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -197,7 +197,11 @@ static int __init __gic_clocksource_init(void) gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); /* Calculate a somewhat reasonable rating value. */ - gic_clocksource.rating = 200 + gic_frequency / 10000000; + if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) + gic_clocksource.rating = 300; /* Good when frequecy is stable */ + else + gic_clocksource.rating = 200; + gic_clocksource.rating += clamp(gic_frequency / 10000000, 0, 99); ret = clocksource_register_hz(&gic_clocksource, gic_frequency); if (ret < 0)