From: Siddhesh Poyarekar Date: Fri, 11 Sep 2020 03:48:07 +0000 (+0530) Subject: [Morello] All remaining load and store instructions X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ccc39bd0955b1b4c8021100a2e41ae9f73036e14;p=thirdparty%2Fbinutils-gdb.git [Morello] All remaining load and store instructions - LDR/STR immediate, indexed and register offset - LDUR/STUR - LDTR/STTR gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (parse_operands, fix_insn): Add A64C_ADDR_SIMM9. (try_to_encode_as_unscaled_ldst): Add capability loads. * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests. * testsuite/gas/aarch64/morello_ldst.d: Likewise. * testsuite/gas/aarch64/morello_ldst.s: Likewise. include/ChangeLog: 2020-10-20 Siddhesh Poyarekar * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9. (aarch64_op): Add OP_STR_POS_2, OP_LDR_POS_2, OP_LDUR_2, OP_STUR_2. opcodes/ChangeLog: 2020-10-20 Siddhesh Poyarekar * aarch64-asm.c (aarch64_ins_addr_simm): Support scaling. * aarch64-dis.c (aarch64_ext_addr_simm): Likewise. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Add A64C_ADDR_SIMM9. * aarch64-tbl.h (aarch64_opcode_table): New instructions. (AARCH64_OPERANDS): New operands. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 345914f0cb2..1f85fddd081 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2020-10-20 Siddhesh Poyarekar + + * config/tc-aarch64.c (parse_operands, fix_insn): Add + A64C_ADDR_SIMM9. + (try_to_encode_as_unscaled_ldst): Add capability loads. + * testsuite/gas/aarch64/morello_ldst-c64.d: Add tests. + * testsuite/gas/aarch64/morello_ldst.d: Likewise. + * testsuite/gas/aarch64/morello_ldst.s: Likewise. + 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (encode_ld_lit_ofs_17): New function. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index cb7034a41b1..e0ee563c66c 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7365,6 +7365,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) /* skip_p */ 0); break; + case AARCH64_OPND_A64C_ADDR_SIMM9: case AARCH64_OPND_ADDR_SIMM9: case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM11: @@ -8857,7 +8858,9 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr) case OP_STRH_POS: new_op = OP_STURH; break; case OP_LDRSH_POS: new_op = OP_LDURSH; break; case OP_LDR_POS: new_op = OP_LDUR; break; + case OP_LDR_POS_2: new_op = OP_LDUR_2; break; case OP_STR_POS: new_op = OP_STUR; break; + case OP_STR_POS_2: new_op = OP_STUR_2; break; case OP_LDRF_POS: new_op = OP_LDURV; break; case OP_STRF_POS: new_op = OP_STURV; break; case OP_LDRSW_POS: new_op = OP_LDURSW; break; @@ -9085,6 +9088,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value) fix_mov_imm_insn (fixP, buf, new_inst, value); break; + case AARCH64_OPND_A64C_ADDR_SIMM9: case AARCH64_OPND_A64C_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: diff --git a/gas/testsuite/gas/aarch64/morello_ldst-c64.d b/gas/testsuite/gas/aarch64/morello_ldst-c64.d index 73cf837d31f..cfc65036043 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst-c64.d +++ b/gas/testsuite/gas/aarch64/morello_ldst-c64.d @@ -50,6 +50,50 @@ Disassembly of section \.text: .*: 22221704 stxp w2, c4, c5, \[c24\] .*: 2222f7e4 stlxp w2, c4, c29, \[csp\] .*: 222277e4 stxp w2, c4, c29, \[csp\] +.*: c27fff04 ldr c4, \[c24, #65520\] +.*: c2400b04 ldr c4, \[c24, #32\] +.*: c2400304 ldr c4, \[c24\] +.*: c23fff04 str c4, \[c24, #65520\] +.*: c2000b04 str c4, \[c24, #32\] +.*: c2000304 str c4, \[c24\] +.*: c27fffe4 ldr c4, \[csp, #65520\] +.*: c2400be4 ldr c4, \[csp, #32\] +.*: c24003e4 ldr c4, \[csp\] +.*: c23fffe4 str c4, \[csp, #65520\] +.*: c2000be4 str c4, \[csp, #32\] +.*: c20003e4 str c4, \[csp\] +.*: a24ff304 ldur c4, \[c24, #255\] +.*: a2501304 ldur c4, \[c24, #-255\] +.*: a2400304 ldur c4, \[c24\] +.*: a2410304 ldur c4, \[c24, #16\] +.*: a24ffb04 ldtr c4, \[c24, #255\] +.*: a2501b04 ldtr c4, \[c24, #-255\] +.*: a2400b04 ldtr c4, \[c24\] +.*: a2410b04 ldtr c4, \[c24, #16\] +.*: a20ff304 stur c4, \[c24, #255\] +.*: a2101304 stur c4, \[c24, #-255\] +.*: a2000304 stur c4, \[c24\] +.*: a2010304 stur c4, \[c24, #16\] +.*: a20ffb04 sttr c4, \[c24, #255\] +.*: a2101b04 sttr c4, \[c24, #-255\] +.*: a2000b04 sttr c4, \[c24\] +.*: a2010b04 sttr c4, \[c24, #16\] +.*: a24ff3e4 ldur c4, \[csp, #255\] +.*: a25013e4 ldur c4, \[csp, #-255\] +.*: a24003e4 ldur c4, \[csp\] +.*: a24103e4 ldur c4, \[csp, #16\] +.*: a24ffbe4 ldtr c4, \[csp, #255\] +.*: a2501be4 ldtr c4, \[csp, #-255\] +.*: a2400be4 ldtr c4, \[csp\] +.*: a2410be4 ldtr c4, \[csp, #16\] +.*: a20ff3e4 stur c4, \[csp, #255\] +.*: a21013e4 stur c4, \[csp, #-255\] +.*: a20003e4 stur c4, \[csp\] +.*: a20103e4 stur c4, \[csp, #16\] +.*: a20ffbe4 sttr c4, \[csp, #255\] +.*: a2101be4 sttr c4, \[csp, #-255\] +.*: a2000be4 sttr c4, \[csp\] +.*: a2010be4 sttr c4, \[csp, #16\] .*: 42df9704 ldp c4, c5, \[c24, #1008\] .*: 42e01704 ldp c4, c5, \[c24, #-1024\] .*: 42c09704 ldp c4, c5, \[c24, #16\] @@ -82,6 +126,30 @@ Disassembly of section \.text: .*: 62201be4 stnp c4, c6, \[csp, #-1024\] .*: 62009be4 stnp c4, c6, \[csp, #16\] .*: 623f1be4 stnp c4, c6, \[csp, #-32\] +.*: a2402f04 ldr c4, \[c24, #32\]! +.*: a2402704 ldr c4, \[c24\], #32 +.*: a2500f04 ldr c4, \[c24, #-4096\]! +.*: a2500704 ldr c4, \[c24\], #-4096 +.*: a24fff04 ldr c4, \[c24, #4080\]! +.*: a24ff704 ldr c4, \[c24\], #4080 +.*: a2002f04 str c4, \[c24, #32\]! +.*: a2002704 str c4, \[c24\], #32 +.*: a2100f04 str c4, \[c24, #-4096\]! +.*: a2100704 str c4, \[c24\], #-4096 +.*: a20fff04 str c4, \[c24, #4080\]! +.*: a20ff704 str c4, \[c24\], #4080 +.*: a2402fe4 ldr c4, \[csp, #32\]! +.*: a24027e4 ldr c4, \[csp\], #32 +.*: a2500fe4 ldr c4, \[csp, #-4096\]! +.*: a25007e4 ldr c4, \[csp\], #-4096 +.*: a24fffe4 ldr c4, \[csp, #4080\]! +.*: a24ff7e4 ldr c4, \[csp\], #4080 +.*: a2002fe4 str c4, \[csp, #32\]! +.*: a20027e4 str c4, \[csp\], #32 +.*: a2100fe4 str c4, \[csp, #-4096\]! +.*: a21007e4 str c4, \[csp\], #-4096 +.*: a20fffe4 str c4, \[csp, #4080\]! +.*: a20ff7e4 str c4, \[csp\], #4080 .*: 62c11303 ldp c3, c4, \[c24, #32\]! .*: 22c11303 ldp c3, c4, \[c24\], #32 .*: 62e01303 ldp c3, c4, \[c24, #-1024\]! @@ -106,6 +174,26 @@ Disassembly of section \.text: .*: 22a017e4 stp c4, c5, \[csp\], #-1024 .*: 629f97e4 stp c4, c5, \[csp, #1008\]! .*: 229f97e4 stp c4, c5, \[csp\], #1008 +.*: a2636b04 ldr c4, \[c24, x3\] +.*: a2636b04 ldr c4, \[c24, x3\] +.*: a2635b04 ldr c4, \[c24, w3, uxtw #4\] +.*: a263db04 ldr c4, \[c24, w3, sxtw #4\] +.*: a263cb04 ldr c4, \[c24, w3, sxtw\] +.*: a2236b04 str c4, \[c24, x3\] +.*: a2236b04 str c4, \[c24, x3\] +.*: a2235b04 str c4, \[c24, w3, uxtw #4\] +.*: a223db04 str c4, \[c24, w3, sxtw #4\] +.*: a223cb04 str c4, \[c24, w3, sxtw\] +.*: a2636be4 ldr c4, \[csp, x3\] +.*: a2636be4 ldr c4, \[csp, x3\] +.*: a2635be4 ldr c4, \[csp, w3, uxtw #4\] +.*: a263dbe4 ldr c4, \[csp, w3, sxtw #4\] +.*: a263cbe4 ldr c4, \[csp, w3, sxtw\] +.*: a2236be4 str c4, \[csp, x3\] +.*: a2236be4 str c4, \[csp, x3\] +.*: a2235be4 str c4, \[csp, w3, uxtw #4\] +.*: a223dbe4 str c4, \[csp, w3, sxtw #4\] +.*: a223cbe4 str c4, \[csp, w3, sxtw\] .*: c2d813e1 blr \[csp, #-1024\] .*: c2d7f3e1 blr \[csp, #1008\] .*: c2d033e1 blr \[csp, #16\] diff --git a/gas/testsuite/gas/aarch64/morello_ldst.d b/gas/testsuite/gas/aarch64/morello_ldst.d index e8a4d7281dd..49a57a68c3b 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst.d +++ b/gas/testsuite/gas/aarch64/morello_ldst.d @@ -49,6 +49,50 @@ Disassembly of section \.text: .*: 22221564 stxp w2, c4, c5, \[x11\] .*: 2222f7e4 stlxp w2, c4, c29, \[sp\] .*: 222277e4 stxp w2, c4, c29, \[sp\] +.*: c27ffd64 ldr c4, \[x11, #65520\] +.*: c2400964 ldr c4, \[x11, #32\] +.*: c2400164 ldr c4, \[x11\] +.*: c23ffd64 str c4, \[x11, #65520\] +.*: c2000964 str c4, \[x11, #32\] +.*: c2000164 str c4, \[x11\] +.*: c27fffe4 ldr c4, \[sp, #65520\] +.*: c2400be4 ldr c4, \[sp, #32\] +.*: c24003e4 ldr c4, \[sp\] +.*: c23fffe4 str c4, \[sp, #65520\] +.*: c2000be4 str c4, \[sp, #32\] +.*: c20003e4 str c4, \[sp\] +.*: a24ff164 ldur c4, \[x11, #255\] +.*: a2501164 ldur c4, \[x11, #-255\] +.*: a2400164 ldur c4, \[x11\] +.*: a2410164 ldur c4, \[x11, #16\] +.*: a24ff964 ldtr c4, \[x11, #255\] +.*: a2501964 ldtr c4, \[x11, #-255\] +.*: a2400964 ldtr c4, \[x11\] +.*: a2410964 ldtr c4, \[x11, #16\] +.*: a20ff164 stur c4, \[x11, #255\] +.*: a2101164 stur c4, \[x11, #-255\] +.*: a2000164 stur c4, \[x11\] +.*: a2010164 stur c4, \[x11, #16\] +.*: a20ff964 sttr c4, \[x11, #255\] +.*: a2101964 sttr c4, \[x11, #-255\] +.*: a2000964 sttr c4, \[x11\] +.*: a2010964 sttr c4, \[x11, #16\] +.*: a24ff3e4 ldur c4, \[sp, #255\] +.*: a25013e4 ldur c4, \[sp, #-255\] +.*: a24003e4 ldur c4, \[sp\] +.*: a24103e4 ldur c4, \[sp, #16\] +.*: a24ffbe4 ldtr c4, \[sp, #255\] +.*: a2501be4 ldtr c4, \[sp, #-255\] +.*: a2400be4 ldtr c4, \[sp\] +.*: a2410be4 ldtr c4, \[sp, #16\] +.*: a20ff3e4 stur c4, \[sp, #255\] +.*: a21013e4 stur c4, \[sp, #-255\] +.*: a20003e4 stur c4, \[sp\] +.*: a20103e4 stur c4, \[sp, #16\] +.*: a20ffbe4 sttr c4, \[sp, #255\] +.*: a2101be4 sttr c4, \[sp, #-255\] +.*: a2000be4 sttr c4, \[sp\] +.*: a2010be4 sttr c4, \[sp, #16\] .*: 42df9564 ldp c4, c5, \[x11, #1008\] .*: 42e01564 ldp c4, c5, \[x11, #-1024\] .*: 42c09564 ldp c4, c5, \[x11, #16\] @@ -81,6 +125,30 @@ Disassembly of section \.text: .*: 62201be4 stnp c4, c6, \[sp, #-1024\] .*: 62009be4 stnp c4, c6, \[sp, #16\] .*: 623f1be4 stnp c4, c6, \[sp, #-32\] +.*: a2402d64 ldr c4, \[x11, #32\]! +.*: a2402564 ldr c4, \[x11\], #32 +.*: a2500d64 ldr c4, \[x11, #-4096\]! +.*: a2500564 ldr c4, \[x11\], #-4096 +.*: a24ffd64 ldr c4, \[x11, #4080\]! +.*: a24ff564 ldr c4, \[x11\], #4080 +.*: a2002d64 str c4, \[x11, #32\]! +.*: a2002564 str c4, \[x11\], #32 +.*: a2100d64 str c4, \[x11, #-4096\]! +.*: a2100564 str c4, \[x11\], #-4096 +.*: a20ffd64 str c4, \[x11, #4080\]! +.*: a20ff564 str c4, \[x11\], #4080 +.*: a2402fe4 ldr c4, \[sp, #32\]! +.*: a24027e4 ldr c4, \[sp\], #32 +.*: a2500fe4 ldr c4, \[sp, #-4096\]! +.*: a25007e4 ldr c4, \[sp\], #-4096 +.*: a24fffe4 ldr c4, \[sp, #4080\]! +.*: a24ff7e4 ldr c4, \[sp\], #4080 +.*: a2002fe4 str c4, \[sp, #32\]! +.*: a20027e4 str c4, \[sp\], #32 +.*: a2100fe4 str c4, \[sp, #-4096\]! +.*: a21007e4 str c4, \[sp\], #-4096 +.*: a20fffe4 str c4, \[sp, #4080\]! +.*: a20ff7e4 str c4, \[sp\], #4080 .*: 62c11163 ldp c3, c4, \[x11, #32\]! .*: 22c11163 ldp c3, c4, \[x11\], #32 .*: 62e01163 ldp c3, c4, \[x11, #-1024\]! @@ -105,6 +173,26 @@ Disassembly of section \.text: .*: 22a017e4 stp c4, c5, \[sp\], #-1024 .*: 629f97e4 stp c4, c5, \[sp, #1008\]! .*: 229f97e4 stp c4, c5, \[sp\], #1008 +.*: a2636964 ldr c4, \[x11, x3\] +.*: a2636964 ldr c4, \[x11, x3\] +.*: a2635964 ldr c4, \[x11, w3, uxtw #4\] +.*: a263d964 ldr c4, \[x11, w3, sxtw #4\] +.*: a263c964 ldr c4, \[x11, w3, sxtw\] +.*: a2236964 str c4, \[x11, x3\] +.*: a2236964 str c4, \[x11, x3\] +.*: a2235964 str c4, \[x11, w3, uxtw #4\] +.*: a223d964 str c4, \[x11, w3, sxtw #4\] +.*: a223c964 str c4, \[x11, w3, sxtw\] +.*: a2636be4 ldr c4, \[sp, x3\] +.*: a2636be4 ldr c4, \[sp, x3\] +.*: a2635be4 ldr c4, \[sp, w3, uxtw #4\] +.*: a263dbe4 ldr c4, \[sp, w3, sxtw #4\] +.*: a263cbe4 ldr c4, \[sp, w3, sxtw\] +.*: a2236be4 str c4, \[sp, x3\] +.*: a2236be4 str c4, \[sp, x3\] +.*: a2235be4 str c4, \[sp, w3, uxtw #4\] +.*: a223dbe4 str c4, \[sp, w3, sxtw #4\] +.*: a223cbe4 str c4, \[sp, w3, sxtw\] .*: c2d813e1 blr \[csp, #-1024\] .*: c2d7f3e1 blr \[csp, #1008\] .*: c2d033e1 blr \[csp, #16\] diff --git a/gas/testsuite/gas/aarch64/morello_ldst.s b/gas/testsuite/gas/aarch64/morello_ldst.s index e6aa7d6af50..6de19b0e6a1 100644 --- a/gas/testsuite/gas/aarch64/morello_ldst.s +++ b/gas/testsuite/gas/aarch64/morello_ldst.s @@ -69,6 +69,27 @@ morello_stp_base c4, c29, SP_ // Base + immediate offset + .macro morello_uimm ct, xnsp + .irp op, ldr, str + \op \ct, [\xnsp, #65520] + \op \ct, [\xnsp, #32] + \op \ct, [\xnsp, #0] + .endr + .endm +morello_uimm c4, VAREG +morello_uimm c4, SP_ + + .macro morello_simm ct, xnsp + .irp op, ldur, ldtr, stur, sttr + \op \ct, [\xnsp, #255] + \op \ct, [\xnsp, #-255] + \op \ct, [\xnsp, #0] + \op \ct, [\xnsp, #16] + .endr + .endm +morello_simm c4, VAREG +morello_simm c4, SP_ + .macro morello_simm_pair ct, ct2, xnsp .irp op, ldp, stp, ldnp, stnp \op \ct, \ct2, [\xnsp, #1008] @@ -82,6 +103,19 @@ morello_simm_pair c4, c6, SP_ // Indexed + .macro morello_index ct, xnsp + .irp op, ldr, str + \op \ct, [\xnsp, #32]! + \op \ct, [\xnsp], #32 + \op \ct, [\xnsp, #-4096]! + \op \ct, [\xnsp], #-4096 + \op \ct, [\xnsp, #4080]! + \op \ct, [\xnsp], #4080 + .endr + .endm +morello_index c4, VAREG +morello_index c4, SP_ + .macro morello_index_pair ct, ct2, xnsp .irp op, ldp, stp \op \ct, \ct2, [\xnsp, #32]! @@ -95,6 +129,20 @@ morello_simm_pair c4, c6, SP_ morello_index_pair c3, c4, VAREG morello_index_pair c4, c5, SP_ +// Register offset. + + .macro morello_regoff ct, xnsp, off + .irp op, ldr, str + \op \ct, [\xnsp, x\off] + \op \ct, [\xnsp, x\off, lsl #0] + \op \ct, [\xnsp, w\off, uxtw #4] + \op \ct, [\xnsp, w\off, sxtw #4] + \op \ct, [\xnsp, w\off, sxtw] + .endr + .endm +morello_regoff c4, VAREG, 3 +morello_regoff c4, SP_, 3 + // Branch and Load, Prefetch, etc. .macro morello_branch_load cnsp diff --git a/include/ChangeLog b/include/ChangeLog index 4604eaece79..710db31c272 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2020-10-20 Siddhesh Poyarekar + + * opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9. + (aarch64_op): Add OP_STR_POS_2, OP_LDR_POS_2, OP_LDUR_2, + OP_STUR_2. + 2020-10-20 Siddhesh Poyarekar * elf/aarch64.h: New relocation R_MORELLO_LD_PREL_LO17. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 716e0e3b34e..4366b2a2d68 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -530,6 +530,7 @@ enum aarch64_opnd BLR/BR. */ AARCH64_OPND_CAPADDR_SIMPLE, /* Simple base address with no offset. */ AARCH64_OPND_A64C_ADDR_SIMM7, /* Address with 7-bit immediate offset. */ + AARCH64_OPND_A64C_ADDR_SIMM9, /* Address with 9-bit immediate offset. */ AARCH64_OPND_ADDR_PCREL17, /* 17-bit PC-relative address for e.g. LDR. */ }; @@ -743,6 +744,8 @@ enum aarch64_op OP_LDRSH_POS, OP_STR_POS, OP_LDR_POS, + OP_STR_POS_2, + OP_LDR_POS_2, OP_STRF_POS, OP_LDRF_POS, OP_LDRSW_POS, @@ -756,6 +759,8 @@ enum aarch64_op OP_LDURSH, OP_STUR, OP_LDUR, + OP_LDUR_2, + OP_STUR_2, OP_STURV, OP_LDURV, OP_LDURSW, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 64979cf399f..5cdc946836c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2020-10-20 Siddhesh Poyarekar + + * aarch64-asm.c (aarch64_ins_addr_simm): Support scaling. + * aarch64-dis.c (aarch64_ext_addr_simm): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p, + aarch64_print_operand): Add A64C_ADDR_SIMM9. + * aarch64-tbl.h (aarch64_opcode_table): New instructions. + (AARCH64_OPERANDS): New operands. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + 2020-10-20 Siddhesh Poyarekar * aarch64-asm-2.c: Regenerate. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 742e5265d33..f96cdf87c9b 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -703,9 +703,10 @@ aarch64_ins_addr_simm (const aarch64_operand *self, insert_field (FLD_Rn, code, info->addr.base_regno, 0); /* simm (imm9 or imm7) */ imm = info->addr.offset.imm; - if (self->fields[0] == FLD_imm7 - || self->fields[0] == FLD_capaddr_simm7 - || info->qualifier == AARCH64_OPND_QLF_imm_tag) + if (operand_need_shift_by_four (self)) + imm >>= 4; + else if (self->fields[0] == FLD_imm7 + || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions.. */ imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier)); insert_field (self->fields[0], code, imm, 0); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 0ad4e3759a4..5d0fb4e2436 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1151,9 +1151,10 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, /* simm (imm9 or imm7) */ imm = extract_field (self->fields[0], code, 0); info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1); - if (self->fields[0] == FLD_imm7 - || self->fields[0] == FLD_capaddr_simm7 - || info->qualifier == AARCH64_OPND_QLF_imm_tag) + if (operand_need_shift_by_four (self)) + info->addr.offset.imm <<= 4; + else if (self->fields[0] == FLD_imm7 + || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions. */ info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); /* qualifier */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 44f69cdbd6b..e8d4f7451a3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1772,6 +1772,23 @@ operand_general_constraint_met_p (aarch64_feature_set features, } break; + case AARCH64_OPND_A64C_ADDR_SIMM9: + /* Scaled signed 9 bits immediate offset. This is currently only + used for cpability load/stores. */ + size = aarch64_get_qualifier_esize (opnd->qualifier); + if (!value_in_range_p (opnd->addr.offset.imm, -256 * size, 255 * size)) + { + set_offset_out_of_range_error (mismatch_detail, idx, + -256 * size, 255 * size); + return 0; + } + if (!value_aligned_p (opnd->addr.offset.imm, size)) + { + set_unaligned_error (mismatch_detail, idx, size); + return 0; + } + break; + case AARCH64_OPND_ADDR_SIMM9_2: /* Unscaled signed 9 bits immediate offset, which has to be negative or unaligned. */ @@ -3974,6 +3991,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, (buf, size, opnd, get_cap_reg_name (opnd->addr.base_regno, 1)); break; + case AARCH64_OPND_A64C_ADDR_SIMM9: case AARCH64_OPND_A64C_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM7: case AARCH64_OPND_ADDR_SIMM9: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index dbfbf440410..5cb8d9ee2ec 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4212,6 +4212,16 @@ const struct aarch64_opcode aarch64_opcode_table[] = A64C_INSN ("stp", 0x22800000, 0xbfc00000, ldstpair_indexed, 0, OP3 (Cat, Cat2, A64C_ADDR_SIMM7), QL3_A64C_CA_CA_ADDR, 0), A64C_INSN ("ldr", 0x82000000, 0xffc00000, loadlit, OP_LDR_LIT_2, OP2 (Cat, ADDR_PCREL17), QL2_A64C_CA_PCREL, 0), + A64C_INSN ("ldr", 0xc2400000, 0xffc00000, ldst_pos, OP_LDR_POS_2, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("str", 0xc2000000, 0xffc00000, ldst_pos, OP_STR_POS_2, OP2 (Cat, ADDR_UIMM12), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("ldr", 0xa2400400, 0xffe00400, ldst_imm9, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("str", 0xa2000400, 0xffe00400, ldst_imm9, 0, OP2 (Cat, A64C_ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("ldr", 0xa2600800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("str", 0xa2200800, 0xffe00c00, ldst_regoff, 0, OP2 (Cat, ADDR_REGOFF), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("ldtr", 0xa2400800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("sttr", 0xa2000800, 0xffe00c00, ldst_unpriv, 0, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("ldur", 0xa2400000, 0xffe00c00, ldst_unscaled, OP_LDUR_2, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), + A64C_INSN ("stur", 0xa2000000, 0xffe00c00, ldst_unscaled, OP_STUR_2, OP2 (Cat, ADDR_SIMM9), QL2_A64C_CA_ADDR, 0), A64C_INSN ("ldct", 0xc2c4b000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0), A64C_INSN ("stct", 0xc2c49000, 0xfffffc00, a64c, 0, OP2 (Rt, ADDR_SIMPLE), QL2_A64C_X_ADDR, 0), @@ -6182,12 +6192,16 @@ const struct aarch64_opcode aarch64_opcode_table[] = "6-bit unsigned immediate") \ Y(PERM, perm, "PERM", 0, F(), "a capability permission") \ Y(FORM, form, "FORM", 0, F(), "a capability form") \ - Y(ADDRESS, addr_simm, "CAPADDR_SIMM7", 0, F(FLD_capaddr_simm7), \ + Y(ADDRESS, addr_simm, "CAPADDR_SIMM7", OPD_F_SHIFT_BY_4, \ + F(FLD_capaddr_simm7), \ "a capability based address with 7-bit signed immediate offset") \ Y(ADDRESS, addr_simple, "CAPADDR_SIMPLE", 0, F(), \ "a capability address with base register (no offset)") \ Y(ADDRESS, addr_simm, "A64C_ADDR_SIMM7", 0, \ F(FLD_imm7,FLD_a64c_index2), \ "an address with 7-bit signed immediate offset") \ + Y(ADDRESS, addr_simm, "A64C_ADDR_SIMM9", OPD_F_SHIFT_BY_4, \ + F(FLD_imm9,FLD_index), \ + "an address with 7-bit signed immediate offset") \ Y(ADDRESS, imm, "ADDR_PCREL17", OPD_F_SEXT | OPD_F_SHIFT_BY_4, \ F(FLD_imm17), "17-bit PC-relative address")