From: Richard Earnshaw Date: Fri, 8 Dec 2023 16:04:18 +0000 (+0000) Subject: Revert "arm: vld1q_types_x3 ACLE intrinsics" X-Git-Tag: basepoints/gcc-15~3802 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=ccc6226e57bae9727fae4b858b6dee8adfc02577;p=thirdparty%2Fgcc.git Revert "arm: vld1q_types_x3 ACLE intrinsics" This reverts commit 2514a331835e055a963fd059dc5770e5ae500af0. --- diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 557873ac0285..3eb41c6bdc83 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10412,15 +10412,6 @@ vld1q_p64_x2 (const poly64_t * __a) return __rv.__i; } -__extension__ extern __inline poly64x2x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_p64_x3 (const poly64_t * __a) -{ - union { poly64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); - return __rv.__i; -} - #pragma GCC pop_options __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10486,42 +10477,6 @@ vld1q_s64_x2 (const int64_t * __a) return __rv.__i; } -__extension__ extern __inline int8x16x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_s8_x3 (const uint8_t * __a) -{ - union { int8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); - return __rv.__i; -} - -__extension__ extern __inline int16x8x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_s16_x3 (const uint16_t * __a) -{ - union { int16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); - return __rv.__i; -} - -__extension__ extern __inline int32x4x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_s32_x3 (const int32_t * __a) -{ - union { int32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); - return __rv.__i; -} - -__extension__ extern __inline int64x2x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_s64_x3 (const int64_t * __a) -{ - union { int64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); - return __rv.__i; -} - #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10558,26 +10513,6 @@ vld1q_f32_x2 (const float32_t * __a) return __rv.__i; } -#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) -__extension__ extern __inline float16x8x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_f16_x3 (const float16_t * __a) -{ - union { float16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hf (__a); - return __rv.__i; -} -#endif - -__extension__ extern __inline float32x4x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_f32_x3 (const float32_t * __a) -{ - union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4sf ((const __builtin_neon_sf *) __a); - return __rv.__i; -} - __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8 (const uint8_t * __a) @@ -10642,42 +10577,6 @@ vld1q_u64_x2 (const uint64_t * __a) return __rv.__i; } -__extension__ extern __inline uint8x16x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_u8_x3 (const uint8_t * __a) -{ - union { uint8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); - return __rv.__i; -} - -__extension__ extern __inline uint16x8x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_u16_x3 (const uint16_t * __a) -{ - union { uint16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); - return __rv.__i; -} - -__extension__ extern __inline uint32x4x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_u32_x3 (const uint32_t * __a) -{ - union { uint32x4x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v4si ((const __builtin_neon_si *) __a); - return __rv.__i; -} - -__extension__ extern __inline uint64x2x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_u64_x3 (const uint64_t * __a) -{ - union { uint64x2x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v2di ((const __builtin_neon_di *) __a); - return __rv.__i; -} - __extension__ extern __inline poly8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8 (const poly8_t * __a) @@ -10710,24 +10609,6 @@ vld1q_p16_x2 (const poly16_t * __a) return __rv.__i; } -__extension__ extern __inline poly8x16x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_p8_x3 (const poly8_t * __a) -{ - union { poly8x16x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v16qi ((const __builtin_neon_qi *) __a); - return __rv.__i; -} - -__extension__ extern __inline poly16x8x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_p16_x3 (const poly16_t * __a) -{ - union { poly16x8x3_t __i; __builtin_neon_ci __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8hi ((const __builtin_neon_hi *) __a); - return __rv.__i; -} - __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_lane_s8 (const int8_t * __a, int8x8_t __b, const int __c) @@ -20029,15 +19910,6 @@ vld1q_bf16_x2 (const bfloat16_t * __ptr) return __rv.__i; } -__extension__ extern __inline bfloat16x8x3_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vld1q_bf16_x3 (const bfloat16_t * __ptr) -{ - union { bfloat16x8x3_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x3v8bf ((const __builtin_neon_bf *) __ptr); - return __rv.__i; -} - __extension__ extern __inline bfloat16x4x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld2_bf16 (bfloat16_t const * __ptr) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index a363bf18ccb7..6a8f0cb2ce1f 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -302,7 +302,6 @@ VAR13 (LOAD1, vld1, v8qi, v4hi, v4hf, v2si, v2sf, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) -VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR12 (LOAD1LANE, vld1_lane, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di, v4bf, v8bf) VAR10 (LOAD1, vld1_dup, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index b37d95f1fa07..55049ea549f3 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4967,33 +4967,6 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_load1_2reg")] ) -(define_insn "neon_vld1_x3" - [(set (match_operand:CI 0 "s_register_operand" "=w") - (unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um") - (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - UNSPEC_VLD3A))] - "TARGET_NEON" -{ - int regno = REGNO (operands[0]); - rtx ops[4]; - ops[0] = gen_rtx_REG (DImode, regno); - ops[1] = gen_rtx_REG (DImode, regno + 2); - ops[2] = gen_rtx_REG (DImode, regno + 4); - ops[3] = operands[1]; - - output_asm_insn ("vld1.\t{%P0, %P1, %P2}, %A3", ops); - - ops[0] = gen_rtx_REG (DImode, regno + 6); - ops[1] = gen_rtx_REG (DImode, regno + 8); - ops[2] = gen_rtx_REG (DImode, regno + 10); - ops[3] = operands[1]; - - output_asm_insn ("vld1.\t{%P0, %P1, %P2}, %A3", ops); - return ""; -} - [(set_attr "type" "neon_load1_3reg")] -) - ;; The lane numbers in the RTL are in GCC lane order, having been flipped ;; in arm_expand_neon_args. The lane numbers are restored to architectural ;; lane order here. diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c index bfad282751b4..1d31777afdf3 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c @@ -60,69 +60,8 @@ poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a) return vld1q_p16_x2 (a); } -uint8x16x3_t test_vld1q_u8_x3 (uint8_t * a) -{ - return vld1q_u8_x3 (a); -} - -uint16x8x3_t test_vld1q_u16_x3 (uint16_t * a) -{ - return vld1q_u16_x3 (a); -} - -uint32x4x3_t test_vld1q_u32_x3 (uint32_t * a) -{ - return vld1q_u32_x3 (a); -} - -uint64x2x3_t test_vld1q_u64_x3 (uint64_t * a) -{ - return vld1q_u64_x3 (a); -} - -int8x16x3_t test_vld1q_s8_x3 (int8_t * a) -{ - return vld1q_s8_x3 (a); -} - -int16x8x3_t test_vld1q_s16_x3 (int16_t * a) -{ - return vld1q_s16_x3 (a); -} - -int32x4x3_t test_vld1q_s32_x3 (int32_t * a) -{ - return vld1q_s32_x3 (a); -} - -int64x2x3_t test_vld1q_s64_x3 (int64_t * a) -{ - return vld1q_s64_x3 (a); -} - -float32x4x3_t test_vld1q_f32_x3 (float32_t * a) -{ - return vld1q_f32_x3 (a); -} - -poly8x16x3_t test_vld1q_p8_x3 (poly8_t * a) -{ - return vld1q_p8_x3 (a); -} - -poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a) -{ - return vld1q_p16_x3 (a); -} - /* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ - /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ - /* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ -/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ - /* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ + diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c index 4138fe951ee7..5f6fc98640e7 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c @@ -10,10 +10,4 @@ bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a) return vld1q_bf16_x2 (a); } -bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a) -{ - return vld1q_bf16_x3 (a); -} - /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c index 01640d7cc1f6..aecf491a4de8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c @@ -10,10 +10,5 @@ float16x8x2_t test_vld1q_f16_x2 (float16_t * a) return vld1q_f16_x2 (a); } -float16x8x3_t test_vld1q_f16_x3 (float16_t * a) -{ - return vld1q_f16_x3 (a); -} - /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ -/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ + diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c index ae2ab36df57c..04ceb5e4a247 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c @@ -10,10 +10,5 @@ poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a) return vld1q_p64_x2 (a); } -poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a) -{ - return vld1q_p64_x3 (a); -} - /* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ -/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +