From: Matt Roper Date: Fri, 24 Apr 2026 20:48:19 +0000 (-0700) Subject: drm/xe: Drop xe_hw_engine_mmio_write32() X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=cd2f1b4462c05bfe7610edb8cde6f084c3a4d6d1;p=thirdparty%2Fkernel%2Flinux.git drm/xe: Drop xe_hw_engine_mmio_write32() xe_hw_engine_mmio_write32() is only used in a single place and is easily replaced by a regular xe_mmio_write32() call. Register read/write interfaces are already complicated enough with MCR vs non-MCR handling, so we should avoid adding extra wrappers that just make it more confusing what to use. xe_hw_engine_mmio_write32() did have a forcewake assertion that we're dropping here, but that assertion wasn't entirely correct anyway. It was checking hwe->domain which is currently set to XE_FW_RENDER for the BCS engine, even though BCS engines reside in the GT domain. v2: - Drop prototype in header file as well. (Shuicheng) Cc: Shuicheng Lin Reviewed-by: Shuicheng Lin Link: https://patch.msgid.link/20260424-engine-setup-v2-9-59cc620a25f1@intel.com Signed-off-by: Matt Roper --- diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 91e644067cc42..b3da832a54145 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -282,27 +282,6 @@ static void hw_engine_fini(void *arg) hwe->gt = NULL; } -/** - * xe_hw_engine_mmio_write32() - Write engine register - * @hwe: engine - * @reg: register to write into - * @val: desired 32-bit value to write - * - * This function will write val into an engine specific register. - * Forcewake must be held by the caller. - * - */ -void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, - struct xe_reg reg, u32 val) -{ - xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); - xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); - - reg.addr += hwe->mmio_base; - - xe_mmio_write32(&hwe->gt->mmio, reg, val); -} - /** * xe_hw_engine_mmio_read32() - Read engine register * @hwe: engine @@ -325,8 +304,8 @@ u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) { - xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0), - xe_bo_ggtt_addr(hwe->hwsp)); + xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base), + xe_bo_ggtt_addr(hwe->hwsp)); } static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe, diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h index 6b5f9fa2a5948..ee9218773b51a 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.h +++ b/drivers/gpu/drm/xe/xe_hw_engine.h @@ -76,7 +76,6 @@ const char *xe_hw_engine_class_to_str(enum xe_engine_class class); u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe); enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe); -void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val); u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg); #endif